Search results for "voltage overshoot"

Found 8 publication records. Showing 8 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Jason Cong, Cheng-Kok Koh	Interconnect layout optimization under higher-order RLC model.	ICCAD	1997	DBLP DOI BibTeX RDF	RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
1	Abinash Roy, Masud H. Chowdhury	Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects.	ISCAS	2008	DBLP DOI BibTeX RDF
1	D. Trémouilles, Steven Thijs, Philippe Roussel, M. I. Natarajan, Vesselin K. Vassilev, Guido Groeseneken	Transient voltage overshoot in TLP testing - Real or artifact?	Microelectronics Reliability	2007	DBLP DOI BibTeX RDF
1	Stephen Coombes, Yulia Timofeeva, Carl-Magnus Svensson, Gabriel J. Lord, Kresimir Josic, S. J. Cox, C. M. Colbert	Branching dendrites with resonant membrane: a "sum-over-trips" approach.	Biological Cybernetics	2007	DBLP DOI BibTeX RDF	Quasi-active membrane, “Sum-over-trips”, Cable theory, Dendrites
1	Harald Gossner	ESD protection for the deep sub micron regime - a challenge for design methodology.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester	Optimal Inductance for On-chip RLC Interconnections.	ICCD	2003	DBLP DOI BibTeX RDF
1	Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl	A physical model for the transient response of capacitively loaded distributed rlc interconnects.	DAC	2002	DBLP DOI BibTeX RDF	distributed rlc lines, overshoot, interconnects, crosstalk, time delay, repeaters, transient response
1	Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo	Interconnect design for deep submicron ICs.	ICCAD	1997	DBLP DOI BibTeX RDF	required-arrival-time Steiner tree higher-order moment signal delay and integrity

Displaying result #1 - #8 of 8 (100 per page; Change: )