Search results for "voltage variation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Nigel Drego, Anantha Chandrakasan, Duane S. Boning	A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays.	ISQED	2007	DBLP DOI BibTeX RDF
2	Brian Greskamp, Smruti R. Sarangi, Josep Torrellas	Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Mark M. Budnik, Kaushik Roy	A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
2	Mark M. Budnik, Kaushik Roy	Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network.	DATE	2006	DBLP DOI BibTeX RDF
2	Ilias Pappas, L. Nalpantidis, Vasilios Kalenteridis, Stilianos Siskos, Alkis A. Hatzopoulos, C. A. Dimitriadis	A threshold voltage variation cancellation technique for analogue peripheral circuits of a display array using poly-Si TFTs.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Howard Chen, Daniel L. Ostapko	Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis.	PATMOS	2004	DBLP DOI BibTeX RDF
2	Ed Grochowski, David Ayers, Vivek Tiwari	Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation.	HPCA	2002	DBLP DOI BibTeX RDF	Power delivery, supply voltage drop, simulation, microprocessor, inductive noise, di/dt
1	Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata	Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Shakeb A. Khan, Tarikul Islam	Precision Active Bridge Circuit for Measuring Incremental Resistance with ANN Compensation of Excitation Voltage Variation.	J. Sensor Technology	2011	DBLP DOI BibTeX RDF
1	Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici	Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing.	J. Low Power Electronics	2011	DBLP DOI BibTeX RDF
1	Mehdi Terosiet, Sylvain Feruglio, Farouk Vallette, Patrick Garda, Olivier Romain, Julien Le Kernec	A self-sufficient digitally controlled ring oscillator compensated for supply voltage variation.	ICECS	2011	DBLP DOI BibTeX RDF
1	Krishan Gopal Verma, Brajesh Kumar Kaushik, Raghuvir Singh	Propagation Delay Variation due to Process Induced Threshold Voltage Variation.	ICT	2010	DBLP DOI BibTeX RDF
1	Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark	In-situ characterization and extraction of SRAM variability.	DAC	2010	DBLP DOI BibTeX RDF	SRAM test, data retention voltage, threshold voltage variation, write margin, extraction
1	Byung-Tae Choi, Hyung Dal Park, Heung-Sik Tae	Effects of Address-on-Time on Wall Voltage Variation during Address-Period in AC Plasma Display Panel.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Yu Wang 0002, Xukai Shen, Rong Luo, Huazhong Yang	Leakage Power Reduction through Dual Vth Assignment Considering Threshold voltage Variation.	Journal of Circuits, Systems, and Computers	2009	DBLP DOI BibTeX RDF
1	Yun Ye, Frank Liu, Min Chen, Yu Cao	Variability analysis under layout pattern-dependent rapid-thermal annealing process.	DAC	2009	DBLP DOI BibTeX RDF	dopant activation, layout pattern, rapid-thermal annealing, threshold voltage variation, physical design
1	Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar	Reducing peak power with a table-driven adaptive processor core.	MICRO	2009	DBLP DOI BibTeX RDF	resource resizing, voltage variation, peak power, adaptive architectures, decoupling capacitance
1	Andre Mansano, Andre Vilas Boas, Alfredo Olmos, Jefferson Soldera	Zero quiescent current startup circuit with automatic turning-off for low power current and voltage reference.	SBCCI	2009	DBLP DOI BibTeX RDF	power-up, starter, initialization, start-up, current reference
1	Kameswar Rao Vaddina, Ethiopia Nigussie, Pasi Liljeberg, Juha Plosila	Self-timed thermal sensing and monitoring of multicore systems.	DDECS	2009	DBLP DOI BibTeX RDF
1	Ratul Kumar Baruah, Santanu Mahapatra	Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	K. C. Narasimhamurthy, Roy P. Paily	Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Sanjay Kumar Wadhwa	A Low Voltage CMOS Proportional-to-Absolute Temperature Current Reference.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Byoung-Mo Moon, Young-June Park, Deog-Kyoon Jeong	Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Wei Kong, Paul C. Parries, G. Wang, Subramanian S. Iyer	Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation.	ITC	2008	DBLP DOI BibTeX RDF
1	Yibo Wang, Yici Cai, Xianlong Hong	A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
1	Takashi Enami, Shinyu Ninomiya, Masanori Hashimoto	Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise.	ISPD	2008	DBLP DOI BibTeX RDF	principal component analysis, gaussianization, power supply noise, statistical timing analysis
1	Patrick McGuinness	Variations, margins, and statistics.	ISPD	2008	DBLP DOI BibTeX RDF	design margins, process variations, yield, SSTA
1	Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng	Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.	DATE	2008	DBLP DOI BibTeX RDF
1	Hung-Wei Chen, Jing-Yu Luo, Wen-Cheng Yen	A 1V power supply operation CMOS subbandgap reference using switched capacitors.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Man Kay Law, Amine Bermak	A Time Domain differential CMOS Temperature Sensor with Reduced Supply Sensitivity.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Sanjay Kumar Wadhwa	A low voltage CMOS bandgap reference circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Seiede Fateme Ashrafi, Seyed Mojtaba Atarodi, Mohammad Chahardori	New low voltage, high PSRR, CMOS bandgap voltage reference.	SoCC	2008	DBLP DOI BibTeX RDF
1	Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown	On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Domenik Helms, Olaf Meyer, Marko Hoyer, Wolfgang Nebel	Voltage- and ABB-island optimization in high level synthesis.	ISLPED	2007	DBLP DOI BibTeX RDF	adaptive body biasing, process variation, leakage, voltage islands
1	Young-Kiu Choi, Byung-Wook Jung	Parameter Tuning for Buck Converters Using Genetic Algorithms.	ICIC	2007	DBLP DOI BibTeX RDF	buck converter, output voltage control, genetic algorithm
1	Wei-Shen Wang, Michael Liu, Michael Orshansky	Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky	Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty.	DAC	2006	DBLP DOI BibTeX RDF
1	Yunfeng Peng, Derui Kong, Feng Zhou	A Low-Voltage Sampling Switch with Improved Linearity.	CCECE	2006	DBLP DOI BibTeX RDF
1	Mohankumar N. Somasundaram, Dongsheng Ma	Integrated low-ripple-voltage fast-response switched-capacitor power converter with interleaving regulation scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Guidong Liu, Wensheng Yu, Zhishou Tu	Power Management for Alleviation of the Impact on PEM Fuel Cell due to Load Fluctuation.	ISDA	2006	DBLP DOI BibTeX RDF
1	Vasily G. Moshnyaga, Tomoyuki Yamanaka	Multiplier Energy Reduction by Dynamic Voltage Variation.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De	Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage.	ISLPED	2005	DBLP DOI BibTeX RDF	Vt mismatch, Vt variation, random dopant variation, threshold voltage variation, transistor mismatch, transistor threshold voltage mismatch, process variation, CMOS, integrated circuits, variation, transistors, threshold voltage, mismatch, body bias, Vt
1	Siva Narendra	Challenges and design choices in nanoscale CMOS.	JETC	2005	DBLP DOI BibTeX RDF	nanoscale, process variation, CMOS, leakage power
1	Hongchin Lin, Chao-Jui Liang	A sub-1V bandgap reference circuit using subthreshold current.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Tomoyuki Yamanaka, Vasily G. Moshnyaga	Reducing multiplier energy by data-driven voltage variation.	ISCAS	2004	DBLP BibTeX RDF
1	Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif	Full chip leakage estimation considering power supply and temperature variations.	ISLPED	2003	DBLP DOI BibTeX RDF	supply voltage variation, leakage power, thermal analysis
1	Saeid Mehrmanesh, Mohammad B. Vahidfar, Hesam Amir Aslanzadeh, Seyed Mojtaba Atarodi	A 1-volt, high PSRR, CMOS bandgap voltage reference.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Siva Narendra, Vivek De, Shekhar Borkar, Dimitri Antoniadis, Anantha Chandrakasan	Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	sub-threshold leakage, CMOS, within-die variation
1	Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu	Test structures for delay variability.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
1	Mario R. Casu, Philippe Flatresse	Converting an Embedded Low-Power SRAM from Bulk to PD-SOI.	MTDT	2002	DBLP DOI BibTeX RDF
1	Sudhakar Bobba, Ibrahim N. Hajj	Maximum voltage variation in the power distribution network of VLSI circuits with RLC models.	ISLPED	2001	DBLP DOI BibTeX RDF
1	Kenneth L. Shepard	CAD Issues for CMOS VLSI Design in SOI.	ISQED	2001	DBLP DOI BibTeX RDF
1	Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi	A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs.	ISLPED	1998	DBLP DOI BibTeX RDF