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Searching for phrase wire-sizing optimization (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1996-2006 (8)
Publication types (Num. hits)
article(5) inproceedings(3)
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Found 8 publication records. Showing 8 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
2Youxin Gao, Martin D. F. Wong Wire-sizing optimization with inductance consideration using transmission-line model. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
2Jason Cong, Cheng-Kok Koh Interconnect layout optimization under higher-order RLC model. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF RATS trees, Steiner routings, bounded-radius Steiner trees, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization, circuit optimisation, topology optimization, delay optimization
1Narender Hanchate, Nagarajan Ranganathan A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Game theory, transmission lines, crosstalk noise, interconnect models, wire sizing, interconnect delay
1Magdy A. El-Moursy, Eby G. Friedman Power characteristics of inductive interconnect. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
1Harshit K. Shah, Pun Shiu, Brian Bell, Mamie Aldredge, Namarata Sopory, Jeff Davis Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects. Search on Bibsonomy ICCAD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Jason Cong, David Zhigang Pan Wire width planning for interconnect performance optimization. Search on Bibsonomy IEEE Trans. on CAD of Integrated Circuits and Systems The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Youxin Gao, D. F. Wong Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
1Qingjian Yu, Ernest S. Kuh, Tianxiong Xue Moment models of general transmission lines with application to interconnect analysis and optimization. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
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