Search results for "write margin"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark	In-situ characterization and extraction of SRAM variability.	DAC	2010	DBLP DOI BibTeX RDF	SRAM test, data retention voltage, threshold voltage variation, write margin, extraction
1	Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda	Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Hongbin Sun, Chuanyin Liu, Nanning Zheng, Tai Min, Tong Zhang	Design techniques to improve the device write margin for MRAM-based cache memory.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Andrew Carlson, Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolic	SRAM Read/Write Margin Enhancements Using FinFETs.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara	A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Tuan Vu Cao	Improved write margin 6T-SRAM for low supply voltage applications.	SoCC	2009	DBLP DOI BibTeX RDF
1	S. Lakshminarayanan, J. Joung, G. Narasimhan, R. Kapre, M. Slanina, J. Tung, M. Whately, C.-L. Hou, W.-J. Liao, S.-C. Lin, P.-G. Ma, C.-W. Fan, M.-C. Hsieh, F.-C. Liu, K.-L. Yeh, W.-C. Tseng, S. W. Lu	Standby power reduction and SRAM cell optimization for 65nm technology.	ISQED	2009	DBLP DOI BibTeX RDF
1	Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto	A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme.	ISQED	2009	DBLP DOI BibTeX RDF
1	Jiajing Wang, Satyanand Nalam, Benton H. Calhoun	Analyzing static and dynamic write margin for nanometer SRAMs.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Bastien Giraud, Amara Amara	Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS.	DELTA	2008	DBLP DOI BibTeX RDF	SRAM cell, Double Gate (DG), Static Noise Margin (SNM), Write Margin (WM)
1	Sherif A. Tawfik, Volkan Kursun	Dynamic wordline voltage swing for low leakage and stable static memory banks.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham	Cache Design for Low Power and High Yield.	ISQED	2008	DBLP DOI BibTeX RDF	reduce voltage swing, sram yield, SRAM 6T cell, cache design, parametric failure
1	Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi	Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Keejong Kim, Hamid Mahmoodi, Kaushik Roy	A low-power SRAM using bit-line charge-recycling technique.	ISLPED	2007	DBLP DOI BibTeX RDF	write margin, write power, low power, process variation, SRAM, charge-recycling
1	Jordan Lai	SRAM Design Techniques for Sub-nano CMOS Technology.	MTDT	2006	DBLP DOI BibTeX RDF
1	Yuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa	MRAM Write Error Categorization with QCKB.	MTDT	2006	DBLP DOI BibTeX RDF