Search results for "write power"

Found 11 publication records. Showing 11 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai	A power-aware SWDR cell for reducing cache write power.	ISLPED	2003	DBLP DOI BibTeX RDF	circuit-level, write power, low power, cache, SRAM
1	Sangyeun Cho, Hyunjin Lee	Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance.	MICRO	2009	DBLP DOI BibTeX RDF	memory write performance, phase-change memory
1	Sherif A. Tawfik, Volkan Kursun	Low power and robust 7T dual-Vt SRAM circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Sherif A. Tawfik, Volkan Kursun	Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation.	ISQED	2008	DBLP DOI BibTeX RDF
1	Keejong Kim, Hamid Mahmoodi, Kaushik Roy	A low-power SRAM using bit-line charge-recycling technique.	ISLPED	2007	DBLP DOI BibTeX RDF	write margin, write power, low power, process variation, SRAM, charge-recycling
1	Jaydeep P. Kulkarni, Keejong Kim, Kaushik Roy	A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.	ISLPED	2007	DBLP DOI BibTeX RDF	low power SRAM, low voltage SRAM, schmitt trigger, subthreshold SRAM, process variations
1	Kazunori Shimizu, Nozomu Togawa, Takeshi Ikenaga, Satoshi Goto	Power-efficient LDPC code decoder architecture.	ISLPED	2007	DBLP DOI BibTeX RDF	FIFO buffer, LDPC decoder, intermediate message compression technique, message-passing schedule, clock gating
1	Byung-Do Yang, Jae-Eun Lee, Jang-Su Kim, Junghyun Cho, Seung-Yun Lee, Byoung-Gon Yu	A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Mohammad Sharifkhani, Manoj Sachdev	A low power SRAM architecture based on segmented virtual grounding.	ISLPED	2006	DBLP DOI BibTeX RDF	static-random access memory, write power reduction, low-power, SRAM, leakage reduction
1	Yen-Jen Chang, Chia-Lin Yang, Feipei Lai	Value-Conscious Cache: Simple Technique for Reducing Cache Access Power.	DATE	2004	DBLP DOI BibTeX RDF
1	Yen-Jen Chang, Feipei Lai, Chia-Lin Yang	Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF

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