Search results for "yield"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
5	Qing Su, Charles Chiang, Jamil Kawa	Hotspot Based Yield Prediction with Consideration of Correlations.	ISQED	2008	DBLP DOI BibTeX RDF	Systematic Yield, DFM (design for manufacturing), correlation, Yield, Hotspot, Yield Prediction
5	Stuart L. Riley	Limitations to Estimating Yield Based on In-Line Defect Measurements. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	Defect-limited yield, Yield estimation, In-line defect measurements, Kill ratio estimation, Defect review sampling, Defect classification, Yield prediction
5	Allan Y. Wong	A Statistical Approach To Identify Semiconductor Process Equipment Related Yield Problems. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	Systematic yield, Random yield, process equipment defect density, Statistical techniques, Yield analysis
4	M. Zhang, M. Z. Li, Gang Liu, M. H. Wang	Yield Mapping in Precision Farming.	CCTA	2007	DBLP DOI BibTeX RDF	yield monitor system, grain flow sensor, yield map, precision agriculture
4	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Yield enhancements of design-specific FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	design-specific FPGA, interconnect faults, interconnect utilization, yield enhancement, yield prediction, structured ASIC, FPGA interconnect
4	Athanasios T. Markinos, T. A. Gemtos, D. Pateras, L. Toulios, G. Zerva, M. Papaeconomou	The influence of cotton variety in the calibration factor of a cotton yield monitor.	Operational Research	2005	DBLP DOI BibTeX RDF	cotton, yield mapping, yield monitor, calibration, varieties
4	Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko	Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA redundancy, interconnect faults, fault tolerance, yield enhancement, interconnect model, yield prediction, catastrophic faults, FPGA interconnect
4	Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov	Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis
4	Tom Thomas, Brian Anthony	Area, Performance, and Yield Implications of Redundancy in On-Chip Caches.	ICCD	1999	DBLP DOI BibTeX RDF	cache, redundancy, microprocessor, yield, SRAM, yield enhancement, microprocessor design, embedded SRAM
4	Sandra Levasseur, Frederic Duvivier	Application of a yield model merging critical areas and defectivity to industrial products. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	industrial products, survey sampling based estimation tool, fabrication process, SGS-Thomson Crolles plant, multiple products, process versions, 0.5 micron, robustness, defectivity, EYES, critical areas, yield model, integrated circuit yield
3	Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram	Dominant critical gate identification for power and yield optimization in logic circuits.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	low-vt, process variations, yield
3	Lin Huang, Qiang Xu	Performance yield-driven task allocation and scheduling for MPSoCs under process variation.	DAC	2010	DBLP DOI BibTeX RDF	performance yield, process variation, task scheduling
3	Fang Gong, Hao Yu, Yiyu Shi, Daesoo Kim, Junyan Ren, Lei He	QuickYield: an efficient global-search based parametric yield estimation with performance constraints.	DAC	2010	DBLP DOI BibTeX RDF	circuit simulation, parametric yield
3	Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya, Yuzi Kanazawa	Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances.	DAC	2010	DBLP DOI BibTeX RDF	analog/mixed-signal, optimization, yield, Pareto-front
3	Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu	Behavior-level yield enhancement approach for large-scaled analog circuits.	DAC	2010	DBLP DOI BibTeX RDF	process variation, analog circuits, yield enhancement
3	Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin	Frequency and yield optimization using power gates in power-constrained designs.	ISLPED	2009	DBLP DOI BibTeX RDF	optimization, yield, power gate, frequency
3	Costas Argyrides, Giorgos Dimosthenous, Dhiraj K. Pradhan, Carlos Arthur Lang Lisbôa, Luigi Carro	Reliability aware yield improvement technique for nanotechnology based circuits.	SBCCI	2009	DBLP DOI BibTeX RDF	reliability, nanotechnology, yield improvement
3	Jin-Tai Yan, Zhi-Wei Chen	Redundant wire insertion for yield improvement.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	redundant wire, routing, yield
3	Michal Wegiel, Chandra Krintz	Dynamic prediction of collection yield for managed runtimes.	ASPLOS	2009	DBLP DOI BibTeX RDF	reference bits, clustering, parallel, concurrent, operating system, garbage collection, yield prediction
3	Yan Li, Vladimir Stojanovic	Yield-driven iterative robust circuit optimization algorithm.	DAC	2009	DBLP DOI BibTeX RDF	robust circuit optimization, variability, yield, analog circuits
3	Yan Pan, Joonho Kong, Serkan Ozdemir, Gokhan Memik, Sung Woo Chung	Selective wordline voltage boosting for caches to manage yield under process variations.	DAC	2009	DBLP DOI BibTeX RDF	access time failure, selective wordline voltage boosting, cache, process variations, yield
3	Junying Sun, Jinliang Huang, Jing Chen, Lihui Wang	Grain Yield Estimating for Hubei Province Using Remote Sensing Data - Take Semilate Rice as an Example.	ESIAT	2009	DBLP DOI BibTeX RDF	Crop yield, Crop yield estimation models using remote sensing data, Productivity zoning, Hubei province
3	Cesare Ferri, Sherief Reda, R. Iris Bahar	Parametric yield management for 3D ICs: Models and strategies for improvement.	JETC	2008	DBLP DOI BibTeX RDF	performance, process variations, leakage, 3D integration, yield management
3	N. Pete Sedcole, Peter Y. K. Cheung	Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations.	TRETS	2008	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modeling, FPGA, Delay, reconfiguration, process variation, yield
3	Kristian Granhaug, Snorre Aunet	Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Subthreshold CMOS, Output-wired redundancy, Yield and defect tolerance
3	Sachin S. Sapatnekar	Building your yield of dreams.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	nanoscale, modeling variations, CMOS, yield, design for manufacturability, DFM
3	Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif	Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.	ISQED	2008	DBLP DOI BibTeX RDF	decoupled design, 8T, 6T, stacked devices, stability, yield, sram, double gate
3	Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham	Cache Design for Low Power and High Yield.	ISQED	2008	DBLP DOI BibTeX RDF	reduce voltage swing, sram yield, SRAM 6T cell, cache design, parametric failure
3	Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy	Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.	DAC	2008	DBLP DOI BibTeX RDF	STT MRAM, yield
3	Mohamed H. Abu-Rahma, Kinshuk Chowdhury, Joseph Wang, Zhiqin Chen, Sei Seung Yoon, Mohab Anis	A methodology for statistical estimation of read access yield in SRAMs.	DAC	2008	DBLP DOI BibTeX RDF	access failure, random variations, memory, variability, statistical modeling, yield, SRAM, worst-case
3	Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni	Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.	DAC	2008	DBLP DOI BibTeX RDF	non-Gaussian, process variations, yield, clock skew scheduling
3	Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao	Dose map and placement co-optimization for timing yield enhancement and leakage power reduction.	DAC	2008	DBLP DOI BibTeX RDF	dose map, placement, timing yield, leakage power reduction
3	Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera	Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, routing, variation, yield enhancement
3	Megat Norulazmi Megat Mohamed Noor, Shaidah Jusoh	Visualizing the Yield Pattern Outcome for Automatic Data Exploration.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	Automatic data exploration, manufactuirng yield predictive system, Data mining, machine learning, data visualization, predictive system
3	Love Singhal, Sejong Oh, Eli Bozorgzadeh	Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	configuration selection, delay budgeting, process variation, task allocation, within-die variation, timing yield
3	Qiang Zhou, Yici Cai, Duo Li, Xianlong Hong	A Yield-Driven Gridless Router.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	gridless routing, integrated circuit layout, critical area, design for yield
3	Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick	Empirical Validation of Yield Recovery Using Idle-Cycle Insertion.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	false failure, ATPG, delay testing, functional test, structural test, IR drop, yield loss
3	Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike	Performance and yield enhancement of FPGAs with within-die variation using multiple configurations.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, configuration, within-die variation, timing yield
3	N. Pete Sedcole, Peter Y. K. Cheung	Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis.	FPGA	2007	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield
3	Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai	DFM/DFY practices during physical designs for timing, signal integrity, and power.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, DFY, dynamic IR drop, process variation, physical designs, DFM, design for manufacturability, signal integrity, timing integrity, yield analysis, design for yield
3	Zhaoliang Pan, Melvin A. Breuer	Estimating Error Rate in Defective Logic Using Signature Analysis.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Binning integrated circuits, effective yield, signature testing, error rate, error tolerance, yield loss
3	Fei Su, Krishnendu Chakrabarty	Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy.	JETC	2006	DBLP DOI BibTeX RDF	space redundancy, reconfiguration, Microfluidics, yield enhancement
3	Adesh Sharma, R. Sharma, H. Kasana	Empirical comparisons of feed-forward connectionist and conventional regression models for prediction of first lactation 305-day milk yield in Karan Fries dairy cows.	Neural Computing and Applications	2006	DBLP DOI BibTeX RDF	Dairy production, Karan Fries cows, 305-day milk yield, Prediction, Radial basis function networks, Connectionist models, Back-propagation networks
3	Song Peng, Rajit Manohar	Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	asynchronous circuits, yield, defect tolerance, 3D integration, self-reconfiguration
3	Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar	Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration.	DAC	2006	DBLP DOI BibTeX RDF	pareto surfaces, performance space, optimization, yield
3	Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles Chiang	An IC manufacturing yield model considering intra-die variations.	DAC	2006	DBLP DOI BibTeX RDF	random variation, systematic variation, CMP, spatial correlation, manufacturing yield
3	M. A. Karim, Saman K. Halgamuge, A. J. R. Smith, Arthur L. Hsu	Manufacturing Yield Improvement by Clustering.	ICONIP	2006	DBLP DOI BibTeX RDF	Clustering quality, Filtration of noisy data, Data mining, Self-organising map, Yield improvement
3	Akhil Garg, Prashant Dubey	Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost.	DFT	2006	DBLP DOI BibTeX RDF	Compression and Yield, Memory, Repair, Fuse
3	Parijat Dube, Yezekael Hayel	A Real-Time Yield Management Framework for E-Services.	CEC/EEE	2006	DBLP DOI BibTeX RDF	discrete choice model, expected delay, price-delay tradeoff, optimization, queueing theory, Yield management
3	Dirk Müller	Optimizing yield in global routing.	ICCAD	2006	DBLP DOI BibTeX RDF	Steiner tree packing, multi-commodity flows, yield optimization, VLSI routing
3	Antonis Papanikolaou, T. Grabner, Miguel Miranda, Philippe Roussel, Francky Catthoor	Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	system exploration, process variability, parametric yield
3	Shishpal Rawat, Raul Camposano, A. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, A. Sharan	DFM: where's the proof of value?	DAC	2006	DBLP DOI BibTeX RDF	ROI, DFM, design for manufacture, OPC, RET, yield optimization, design for yield
3	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	Yield-Driven, False-Path-Aware Clock Skew Scheduling.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	performance-related circuit yield loss, circuit-level parameters, DFM, clock skew scheduling
3	Robert Madge	New test paradigms for yield and manufacturability.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	nanometer-era semiconductor, test paradigm, yield and manufacturability
3	Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green	Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	systematic yield loss, test structure, BEOL, DFM, process monitoring, silicon debug, infrastructure IP
3	Hailong Yao, Yici Cai, Xianlong Hong, Qiang Zhou	Improved multilevel routing with redundant via placement for yield and reliability.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	redundant via, routing, VLSI, DFM, yield enhancement
3	Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen	Multilevel full-chip routing with testability and yield enhancement.	SLIP	2005	DBLP DOI BibTeX RDF	multilevel routing, yield, testability
3	Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director	Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.	DAC	2005	DBLP DOI BibTeX RDF	correlation, variability, yield, leakage
3	Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei	A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis
3	Marco Ottavi, Xiaopeng Wang, Fred J. Meyer, Fabrizio Lombardi	Simulation of reconfigurable memory core yield.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	Markov chain, manufacturability, yield, defect tolerance
3	Farid N. Najm, Noel Menezes	Statistical timing analysis based on a timing yield model.	DAC	2004	DBLP DOI BibTeX RDF	statistical timing analysis, principal components, timing yield
3	Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang	A methodology to improve timing yield in the presence of process variations.	DAC	2004	DBLP DOI BibTeX RDF	timing analysis, gate sizing, timing yield
3	Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester	Parametric yield estimation considering leakage variability.	DAC	2004	DBLP DOI BibTeX RDF	variability, leakage, parametric yield
3	Fred J. Meyer, Nohpill Park	Predicting Defect-Tolerant Yield in the Embedded Core Context.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Yield, integrated circuit, defect tolerance, embedded core
3	Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg	On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	fault diagnosis, yield improvement
3	Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey	Deformations of IC Structure in Test and Yield Learning.	ITC	2003	DBLP DOI BibTeX RDF	yield learning, defect characterization, diagnosis, fault modeling, defects
3	Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah	Statistical timing for parametric yield prediction of digital integrated circuits.	DAC	2003	DBLP DOI BibTeX RDF	statistical timing, yield prediction
3	Vibhu Kalyan	Dynamic Customer Value Management: Asset Values under Demand Uncertainty using Airline Yield Management and Related Techniques.	Information Systems Frontiers	2002	DBLP DOI BibTeX RDF	MAV, value management, asset values, uncertainty, resources, yield management
3	Kassem Saleh, Robert L. Probert, W. Li, W. Fong	An approach for high-yield requirements capture for e-commerce and its application.	Int. J. on Digital Libraries	2002	DBLP DOI BibTeX RDF	High-yield scenarios, Requirements capture approach, UML, Electronic commerce
3	Yervant Zorian	Embedding infrastructure IP for SOC yield improvement.	DAC	2002	DBLP DOI BibTeX RDF	embedded test & repair, semiconductor IP, yield optimization, test resource partitioning
3	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	infant mortality, negative binomial distribution, clustering, reliability, redundancy, yield, defects, defect tolerance, burn-in
3	Tianxu Zhao, Yue Hao, Peijun Ma, Taifeng Chen	Relation between Reliability and Yield of IC's Based on Discrete Defect Distribution Model. (PDF / PS)	DFT	2001	DBLP DOI BibTeX RDF	Distribution of the defect size, Reliability, Yield
3	Israel Koren, Zahava Koren	Incorporating Yield Enhancement into the Floorplanning Process.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	memory ICs, routing complexity, redundancy, microprocessor, Floorplanning, yield
3	Israel Koren	Should Yield be a Design Objective?	ISQED	2000	DBLP DOI BibTeX RDF	routing, floorplanning, yield, compaction, critical area
3	Chaochang Chiu, Jih-Tay Hsu, Chih-Yung Lin	The Application of Genetic Programming in Milk Yield Prediction for Dairy Cows.	Rough Sets and Current Trends in Computing	2000	DBLP DOI BibTeX RDF	dynamic mutation, milk yield prediction, Genetic programming
3	Hugo Cheung, Sandeep K. Gupta	A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study.	VTS	2000	DBLP DOI BibTeX RDF	critical severity, test escape, fault modeling, IDDQ, yield loss
3	Yervant Zorian	Yield Improvement and Repair Trade-Off for Large Embedded Memories.	DATE	2000	DBLP DOI BibTeX RDF	silicon repair, BIST, DFM, Yield improvement
3	Kees Veelenturf	The Road to Better Reliability and Yield Embedded DfM Tools.	DATE	2000	DBLP DOI BibTeX RDF	wire spreading, yield prediction, yield improvement, DfM
3	Chin-Te Kao, Sam Wu, Jwu E. Chen	A case study of failure analysis and guardband determination for a 64M-bit DRAM.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	guardband determination, prevention strategy, test derivation, test cost, 64 Mbit, integrated circuit testing, yield, DRAM, failure analysis, failure analysis, test selection, DRAM chips, product quality, integrated circuit yield, integrated circuit economics
3	Nobuhiro Tomabechi	Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	subsystem-dividing, yield, defect-tolerant, WSI, multi-dimensional
3	Witold A. Pleskacz	Yield Estimation of VLSI Circuits with Downscaled Layouts. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	IC layout scaling, VLSI circuits, critical area, spot defects, manufacturing yield
3	G. S. Samudra, H. M. Chen, D. S. H. Chan, Yaacob Ibrahim	Yield Optimization by Design Centering and Worst-Case Distance Analysis.	ICCD	1999	DBLP DOI BibTeX RDF	worst-case distance, design centering, optimization, VLSI design, parametric yield
3	Sandrine Barberan, Frederic Duvivier	Management of Critical Areas and Defectivity Data for Yield Trend Modeling. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	critical areas, defect analysis, yield modeling
3	Andrea Boni, Andrea Pierazzi	Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCs. (PDF / PS)	DFT	1998	DBLP DOI BibTeX RDF	BiCMOS analog integrated circuits, Monte Carlo methods, Yield optimization, Analog-digital conversion
3	Pascal Bichebois, Pierre Mathery	Analysis of Defect to Yield Correlation on Memories: Method, Algorithms and Limits. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	algorithm, tool, correlation, method, errors, inspection, yield, failure, defect, limits
3	Jeffrey Z. Su, Wayne Wei-Ming Dai	Post-route optimization for improved yield using a rubber-band wiring model.	ICCAD	1997	DBLP DOI BibTeX RDF	Rubber-Band, Topological Wiring Even Wire Distribution, Yield, Design for Manufacturability, Spacing, Bridge Fault, Routability, Critical Area, Layout Optimization, Routing Congestion
3	Gerard A. Allan, Anthony J. Walton	Efficient critical area estimation for arbitrary defect shapes. (PDF / PS)	DFT	1997	DBLP DOI BibTeX RDF	critical area estimation, arbitrary defect shapes, circular defects, elliptical defects, rod shaped defects, arbitrary shaped defects, Edinburgh Yield Estimator, Cadence layout editor, EYE-sampling tool, EYE, EYES, integrated circuit yield, IC layout
3	Dimitris Nikolos, Haridimos T. Vergos	On the Yield of VLSI Processors with on-chip CPU Cache.	EDCC	1996	DBLP DOI BibTeX RDF	Indexing terms On-chip CPU caches, Partially good chips, Fault Tolerance, Yield Enhancement
3	Fran Hanchek, Shantanu Dutt	Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs.	VLSI Design	1996	DBLP DOI BibTeX RDF	circuit reconfiguration, node covering, fault tolerance, field programmable gate array (FPGA), yield improvement
3	Hans T. Heineken, Wojciech Maly	Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs.	ICCAD	1996	DBLP DOI BibTeX RDF	Standard Cell Designs, Synthesis, Interconnects, Manufacturability, Yield
3	Hari Balachandran, D. M. H. Walker	Improvement of SRAM-based failure analysis using calibrated Iddq testing.	VTS	1996	DBLP DOI BibTeX RDF	defect-bitmap dictionary, voltage testing, microprocessor cache memory, integrated circuit testing, calibration, calibration, SRAM, cache storage, failure analysis, failure analysis, IDDQ testing, current testing, defect classification, SRAM chips, integrated circuit yield, integrated circuit yield
3	Kanji Hirabayashi	A parametric yield model.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	AC yield, delay defect, exponential distribution
3	Leendert M. Huisman	Yield fluctuations and defect models.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	chip testing, defect distribution, field failures, clustering, yield, defect coverage
3	Zhan Chen, Israel Koren	Techniques for Yield Enhancement of VLSI Adders.	ASAP	1995	DBLP DOI BibTeX RDF	VLSI yield, VLSI adder, defect tolerance, VLSI layout
3	Steven D. Millman	Improving quality: Yield versus test coverage.	J. Electronic Testing	1994	DBLP DOI BibTeX RDF	quality, Fault modeling, yield, test economics, physical defects
3	Sy-Yen Kuo, W. Kent Fuchs	Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLA's.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	reconfigurable PLAs, spare allocation, circuit density, chip size, fault diagnosis algorithm, computational complexity, fault tolerant computing, fault location, programmable logic arrays, multiple faults, logic arrays, yield enhancement, reconfigurable logic, memory structures, circuit reliability, manufacturing yield
3	Bruno Ciciani	Redundancy effect on yield of binary tree RAMs.	J. Electronic Testing	1991	DBLP DOI BibTeX RDF	semiconductor memory design, VLSI chip design, yield evaluation, Fault-tolerant memories
3	Yinan N. Shen, Fabrizio Lombardi	Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection.	J. Electronic Testing	1990	DBLP DOI BibTeX RDF	redundant memory, diagnosis, yield, repair, WSI
3	James C. Harden, Noel R. Strader II	Architectural Yield Optimization for WSI.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	architectural yield optimisation, integrated circuit yield modeling, computing structures, VLSI, fault tolerant computing, computer architecture, redundancy, failure analysis, wafer-scale integration, circuit reliability
2	Saeed Shamshiri, Kwang-Ting (Tim) Cheng	Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	yield and cost modeling, Fault tolerance, reliability, system on a chip, redundant design