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1953-1960 (28) 1961-1962 (26) 1963-1964 (27) 1965-1966 (25) 1967 (25) 1968 (23) 1969 (23) 1970-1972 (20) 1973 (28) 1974 (65) 1975 (46) 1976 (66) 1977 (49) 1978 (69) 1979 (61) 1980 (82) 1981 (62) 1982 (86) 1983 (98) 1984 (120) 1985 (190) 1986 (168) 1987 (299) 1988 (430) 1989 (457) 1990 (582) 1991 (414) 1992 (511) 1993 (563) 1994 (739) 1995 (991) 1996 (1007) 1997 (1276) 1998 (1394) 1999 (2138) 2000 (2675) 2001 (3359) 2002 (3938) 2003 (4721) 2004 (6381) 2005 (7645) 2006 (9041) 2007 (9383) 2008 (10904) 2009 (7437) 2010 (1341) 2011 (588) 2012 (576) 2013 (581) 2014 (696) 2015 (667) 2016 (499) 2017 (2)
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Found 82632 publication records. Showing 82622 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
7Michiel C. M. Soer, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet A 1.5-to-5.0GHz input-matched +2dBm P1dB all-passive switched-capacitor beamforming receiver front-end in 65nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7Julie R. Hu, Richard C. Ruby, Brian P. Otis A 1.56GHz wide-tuning all digital FBAR-based PLL in 0.13µm CMOS. Search on Bibsonomy CICC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
7Huiying Zhuo, Yu Li, Woogeun Rhee, Zhihua Wang A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS. Search on Bibsonomy VLSI-DAT The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
8Tzu-Chiang Chao, Wei Hwang A 1.7mW all digital phase-locked loop with new gain generator and low power DCO. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Baoyong Chi, Bingxue Shi A 1.8V 2.4GHz CMOS on-chip impedance matching low noise amplifier for WLAN applications. Search on Bibsonomy ISCAS (2) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
2Thomas Janik, Eric Liau, H. Lorenz, Manfred Menke, E. Plaettner, J. Schweden, H. Seitz, E. Vega-Ordonez A 1.8V p(seudo)SRAM using standard 140nm DRAM technology with self adapting clocked standby operation. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Hamid Charkhkar, Alireza Asadi, R. Lotfi A 1.8V, 10-bit, 40MS/s MOSFET-only pipeline analog-to-digital converter. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Sumio Morioka, Akashi Satoh A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1J. Talebzadeh, M. R. Hasanzadeh, Mohammad Yavari, Omid Shoaei A 10-bit 150-MS/s, parallel pipeline A/D converter in 0.6-µm CMOS. Search on Bibsonomy ISCAS (3) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
7Hironobu Akita, Takahisa Yoshimoto, Hirofumi Yamamoto, Nobuaki Matsudaira, Shigeki Ohtsuka, Shinichirou Taguchi A 10-bit fast lock all-digital data recovery with CR oscillator reference for automotive network. Search on Bibsonomy ISCAS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
2Babak Nejati, Omid Shoaei A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-um CMOS. Search on Bibsonomy ISCAS (1) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
1Sumio Morioka, Akashi Satoh A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
7Panduka Wijetunga A 10.0Gb/s all-active LVDS receiver in 0.18µm CMOS technology. Search on Bibsonomy IEICE Electronic Express The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7Saqib Subhan, Eric A. M. Klumperink, Amir Ghaffari, Gerard J. M. Wienk, Bram Nauta A 100-800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving $<-$40 dBc for ALL Harmonics. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF in silico vox, FPGA, speech recognition, DSP
7Young-Sang Kim, Seon-Kyoo Lee, Hong-June Park, Jae-Yoon Sim A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Jesús Ruiz-Amaya, Manuel Delgado-Restituto, Juan Francisco Fernández-Bootello, D. Brandano, R. Castro-López, José Manuel de la Rosa A 12-bit CMOS Current Steering D/A Converter for Embedded Systems. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7Farhad Sheikhhosseini, Abdolreza Nabavi A 120dB all CMOS variable gain amplifier based on new exponential equation. Search on Bibsonomy APCCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
7Sally Safwat, Ezz El-Din O. Hussein, Maged Ghoneima, Yehea I. Ismail A 12Gbps all digital low power SerDes transceiver for on-chip networking. Search on Bibsonomy ISCAS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
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