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Found 84379 publication records. Showing 84368 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
7Shiheng Yang, Jun Yin, Pui-In Mak, Rui P. Martins A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM. Search on Bibsonomy ISSCC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
7Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits. Search on Bibsonomy ISSCC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
7Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ximenes, Robert Bogdan Staszewski A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. Search on Bibsonomy VLSI Circuits The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
7Enrique Prefasi, Eric Gutierrez, Luis Hernández, Susana Patón, S. Walter, U. Gaier A 0.03mm2, 40nm CMOS 1.5GS/s all-digital complementary PWM-GRO. Search on Bibsonomy ICECS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
7Yao-Chia Liu, Wei-Zen Chen, Mao-Hsuan Chou, Tsung-Hsien Tsai, Yen-Wei Lee, Min-Shueh Yuan A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector. Search on Bibsonomy CICC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
7Won-Joo Yun, Hyun-Woo Lee, Dongsuk Shin, Shin-Deok Kang, Ji-Yeon Yang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim 0001, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyang-Hwa Choi, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Ye Seok Yang A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. Search on Bibsonomy ISSCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
7Peyman Ahmadi, Mohammad Hossein Taghavi, Leonid Belostotski, Arjuna Madanayake A 0.13-µm CMOS Current-Mode All-Pass Filter for Multi-GHz Operation. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
7Dongjun Park, Geontae Park, Jongsun Kim A 0.15 to 2.2 GHz all-digital delay-locked loop. Search on Bibsonomy NEWCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
7Jie-Wei Lai, Chi-Hsueh Wang, Kaipon Kao, Anson Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Yuan-Hung Chung, Paul C. P. Liang, Guang-Kaai Dehng, Hung-Sung Li, George Chien, Robert Bogdan Staszewski A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
7Deok-Soo Kim, Heesoo Song, Taeho Kim, Suhwan Kim, Deog-Kyoon Jeong A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
1José M. García-González, Sara Escalera, José Manuel de la Rosa, Oscar Guerra, Fernando Manuel Medeiro Hidalgo, Rocío del Río, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez A 0.35µm CMOS 17-bit@40kS/s sensor A/D interface based on a programmable-gain cascade 2-1 Sigma Delta modulator. Search on Bibsonomy ISCAS (1) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
7Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
7Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Yasuhisa Shimazaki A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS. Search on Bibsonomy VLSIC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Robert Bogdan Staszewski A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference. Search on Bibsonomy ISSCC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
7Wenfeng Zhao, Rui Pan, Yajun Ha, Zhi Yang A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor. Search on Bibsonomy A-SSCC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Michael Trakimas, Sameer R. Sonkusale A 0.5V Bulk-Input Operational Transconductance Amplifier with Improved Common-Mode Feedback. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
7Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. Search on Bibsonomy IEICE Electronic Express The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
7Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7Shailesh Singh Chouhan, Kari Halonen A 0.67-µW 177-ppm/°C All-MOS Current Reference Circuit in a 0.18-µm CMOS Technology. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
7Xiaoyang Wang 0003, Po-Han Peter Wang, Yuan Cao, Patrick P. Mercier A 0.6V 75nW All-CMOS Temperature Sensor With 1.67m°C/mV Supply Sensitivity. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
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