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Found 82223 publication records. Showing 82214 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Sumio Morioka, Akashi Satoh A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
7Panduka Wijetunga A 10.0Gb/s all-active LVDS receiver in 0.18µm CMOS technology. Search on Bibsonomy IEICE Electronic Express The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7Saqib Subhan, Eric A. M. Klumperink, Amir Ghaffari, Gerard J. M. Wienk, Bram Nauta A 100-800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving $<-$40 dBc for ALL Harmonics. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF in silico vox, FPGA, speech recognition, DSP
7Young-Sang Kim, Seon-Kyoo Lee, Hong-June Park, Jae-Yoon Sim A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Jesús Ruiz-Amaya, Manuel Delgado-Restituto, Juan Francisco Fernández-Bootello, D. Brandano, R. Castro-López, José Manuel de la Rosa A 12-bit CMOS Current Steering D/A Converter for Embedded Systems. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7Farhad Sheikhhosseini, Abdolreza Nabavi A 120dB all CMOS variable gain amplifier based on new exponential equation. Search on Bibsonomy APCCAS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
7Sally Safwat, Ezz El-Din O. Hussein, Maged Ghoneima, Yehea I. Ismail A 12Gbps all digital low power SerDes transceiver for on-chip networking. Search on Bibsonomy ISCAS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
7Feng-Wei Kuo, Ron Chen, Kyle Yen, Hsien-Yuan Liao, Chewnpu Jou, Fu-Lung Hsueh, Masoud Babaie, Robert Bogdan Staszewski A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS. Search on Bibsonomy VLSIC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
1Pascal Urard, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Yeo, B. Gupta A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3). Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF DVB-S2, FEC (forward error correction), LDPC
2Chua-Chin Wang, Chi-Chun Huang, Jian-Sing Liou, Kuan-Wen Fang A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal Sensing. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7Wonsik Yu, KwangSeok Kim, SeongHwan Cho A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator. Search on Bibsonomy CICC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
7Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
7Shuo-Hong Hung, Wei-Hao Kao, Kuan-I. Wu, Yi-Wei Huang, Min-Han Hsieh, Charlie Chung-Ping Chen A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique. Search on Bibsonomy ISCAS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
7Gijs Meuleman, Pieter Harpe, Xiongchuan Huang, Arthur H. M. van Roermund A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios. Search on Bibsonomy ISCAS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
7Anup Jyoti Deka, Venkatesh Prasanna A 1Gbps-10 Gbps multi-standard auto-calibrated all digital phase interpolator in 14nm CMOS. Search on Bibsonomy ISCAS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin A 2 Gb/s balanced AES crypto-chip implementation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF AES, rijndael, ASIC implementation
1Yoshiyuki Karuno, Hiroshi Nagamochi A 2-Approximation Algorithm for the Multi-vehicle Scheduling Problem on a Path with Release and Handling Times. Search on Bibsonomy ESA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
2Jieliang Zhou, Xiaotie Deng, Patrick W. Dymond A 2-D Parallel Convex Hull Algorithm with Optimal Communication Phases. Search on Bibsonomy IPPS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
1Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. Search on Bibsonomy ASAP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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