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1953-1960 (28) 1961-1962 (26) 1963-1964 (27) 1965-1966 (25) 1967 (25) 1968 (23) 1969 (23) 1970-1972 (20) 1973 (30) 1974 (66) 1975 (49) 1976 (67) 1977 (52) 1978 (71) 1979 (62) 1980 (83) 1981 (63) 1982 (88) 1983 (100) 1984 (121) 1985 (192) 1986 (171) 1987 (300) 1988 (431) 1989 (458) 1990 (585) 1991 (414) 1992 (511) 1993 (567) 1994 (739) 1995 (993) 1996 (1010) 1997 (1276) 1998 (1396) 1999 (2138) 2000 (2678) 2001 (3360) 2002 (3941) 2003 (4723) 2004 (6387) 2005 (7651) 2006 (9043) 2007 (9387) 2008 (10911) 2009 (7442) 2010 (1345) 2011 (592) 2012 (583) 2013 (587) 2014 (713) 2015 (675) 2016 (645) 2017 (157)
Publication types (Num. hits)
article(18123) book(20) incollection(2726) inproceedings(62121) phdthesis(26) proceedings(34)
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Found 83060 publication records. Showing 83050 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
7Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien Hu A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC. Search on Bibsonomy IEICE Electronic Express The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
7Kuo-Hsing Cheng, Jen-Chieh Liu, Hong-Yi Huang A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7Shailesh Singh Chouhan, Kari Halonen A 0.67-µW 177-ppm/°C All-MOS Current Reference Circuit in a 0.18-µm CMOS Technology. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
7Paul N. Whatmough, George Smart, Shidhartha Das, Yiannis Andreopoulos, David M. Bull A 0.6V all-digital body-coupled wakeup transceiver for IoT applications. Search on Bibsonomy VLSIC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
7Won-Joo Yun, Hiroki Ishikuro, Tadahiro Kuroda A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface. Search on Bibsonomy A-SSCC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
7Jaimin Mehta, Robert B. Staszewski, Oren Eliezer, Sameh Rezeq, Khurram Waheed, Mitch Entezari, Gennady Feygin, Sudheer Vemulapalli, Vasile Zoicas, Chih-Ming Hung, Nathen Barton, Imran Bashir, Kenneth Maggio, Michel Frechette, Meng-Chang Lee, John L. Wallberg, Patrick Cruise, Naveen K. Yanduru A 0.8mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC. Search on Bibsonomy ISSCC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
7Guoying Wu, Deping Huang, Jingxiao Li, Ping Gui, Tianwei Liu, Shita Guo, Rui Wang, Yanli Fan, Sudipto Chakraborty, Mark Morgan A 1-16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
7Kenji Suzuki, Mamoru Ugajin, Mitsuru Harada A 1-Mbps 1.6-µA Active-RFID CMOS LSI for the 300-MHz Frequency Band with an All-Digital RF Transmitting Scheme. Search on Bibsonomy IEICE Transactions The full citation details ... 2011 DBLP  BibTeX  RDF
7Seyed Kasra Garakoui, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet A 1-to-2.5GHz phased-array IC based on gm-RC all-pass time-delay cells. Search on Bibsonomy ISSCC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1M. R. Nabavi A 1-V 12-bit switched-op amp pipelined ADC with power optimization. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7Heesoo Song, Deok-Soo Kim, Do-Hwan Oh, Suhwan Kim, Deog-Kyoon Jeong A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
7Shuai Chen, Hao Li, Liqiong Yang, Zongren Yang, Weiwu Hu, Patrick Yin Chiang A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS. Search on Bibsonomy CICC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
7Cristina Azcona, Belén Calvo, Nicolás Medrano, Santiago Celma, Cecilia Gimeno A 1.2-V 1.35-μW all MOS temperature sensor for wireless sensor networks. Search on Bibsonomy ISCAS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
7Maciej Kurowski A 1.235 lower bound on the number of points needed to draw all n-vertex planar graphs. Search on Bibsonomy Inf. Process. Lett. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
7Benjamin Moss, Chen Sun, Michael Georgas, Jeffrey Shainline, Jason Orcutt, Jonathan Leu, Mark T. Wade, Yu-Hsin Chen, Kareem Nammari, Xiaoxi Wang, Hanqing Li, Rajeev J. Ram, Milos A. Popovic, Vladimir Stojanovic A 1.23pJ/b 2.5Gb/s monolithically integrated optical carrier-injection ring modulator and all-digital driver circuit in commercial 45nm SOI. Search on Bibsonomy ISSCC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang A 1.25 GHz 32-bit tree-structured carry lookahead adder. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
7Chi-Shuang Oulee, Rong-Jyi Yang A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition. Search on Bibsonomy APCCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
7Susan M. Schober, John Choma Jr. A 1.25mW 0.8-28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS. Search on Bibsonomy ISCAS The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
7Yuki Urano, Won-Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. Search on Bibsonomy ISCAS The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
7Davide De Caro, Carlo Alberto Romani, Nicola Petra, Antonio G. M. Strollo, Claudio Parrella A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
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