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1953-1960 (28) 1961-1962 (26) 1963-1964 (27) 1965-1966 (23) 1967 (25) 1968 (23) 1969 (23) 1970-1972 (19) 1973 (28) 1974 (65) 1975 (46) 1976 (66) 1977 (49) 1978 (69) 1979 (61) 1980 (82) 1981 (62) 1982 (86) 1983 (98) 1984 (120) 1985 (190) 1986 (167) 1987 (299) 1988 (430) 1989 (457) 1990 (582) 1991 (413) 1992 (511) 1993 (563) 1994 (739) 1995 (991) 1996 (1007) 1997 (1276) 1998 (1393) 1999 (2138) 2000 (2675) 2001 (3358) 2002 (3935) 2003 (4721) 2004 (6380) 2005 (7643) 2006 (9040) 2007 (9373) 2008 (10901) 2009 (7436) 2010 (1338) 2011 (585) 2012 (573) 2013 (579) 2014 (689) 2015 (652) 2016 (251)
Publication types (Num. hits)
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Found 82320 publication records. Showing 82311 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin A 2 Gb/s balanced AES crypto-chip implementation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF AES, rijndael, ASIC implementation
1Yoshiyuki Karuno, Hiroshi Nagamochi A 2-Approximation Algorithm for the Multi-vehicle Scheduling Problem on a Path with Release and Handling Times. Search on Bibsonomy ESA The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
2Jieliang Zhou, Xiaotie Deng, Patrick W. Dymond A 2-D Parallel Convex Hull Algorithm with Optimal Communication Phases. Search on Bibsonomy IPPS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
1Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. Search on Bibsonomy ASAP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Cameron T. Charles, David J. Allstot A 2-GHz integrated CMOS reflective-type phase shifter with 675° control range. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
2Yeim-Kuan Chang A 2-Level TCAM Architecture for Ranges. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2006 DBLP  DOI  BibTeX  RDF disjoint ranges, contiguous ranges, ranges, TCAM
2Ricardo Moraes, Francisco Vasques, Paulo Portugal A 2-tier architecture to support real-time communication in CSMA-based networks. Search on Bibsonomy NOMS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
7Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
7Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. Search on Bibsonomy ISSCC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
7Minyoung Song, Inhwa Jung, Sudhakar Pamarti, Chulwoo Kim A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
7Jianhui Wu, Zixuan Wang, Chao Chen, Cheng Huang, Meng Zhang A 2.4-GHz All-Digital PLL With a 1-ps Resolution 0.9-mW Edge-Interchanging-Based Stochastic TDC. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
7Liangge Xu, Saska Lindfors, Kari Stadius, Jussi Ryynänen A 2.4-GHz Low-Power All-Digital Phase-Locked Loop. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
7Liangge Xu, Saska Lindfors, Kari Stadius, Jussi Ryynänen A 2.4-GHz low-power all-digital phase-locked loop. Search on Bibsonomy CICC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Vijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Baoyong Chi, Jinke Yao, Shuguang Han, Xiang Xie, Guolin Li, Zhihua Wang A 2.4GHz low power wireless transceiver analog front-end for endoscopy capsule system. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1A. Tamtrakarn, N. Wongkomet A 2.5-V 10-bit 40-MS/S double sampling pipeline A/D converter. Search on Bibsonomy APCCAS (2) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
7Richard Su, Steven Lanzisera, Kristofer S. J. Pister A 2.6psrms-period-jitter 900MHz all-digital fractional-N PLL built with standard cells. Search on Bibsonomy ESSCIRC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
7Mohammed Abdulaziz, Muhammad Shakir, Ping Lu, Pietro Andreani A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS. Search on Bibsonomy NORCHIP The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Angelo Nagari, Germano Nicollini A 2.7V 350muW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
7Do-Hwan Oh, Deok-Soo Kim, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO. Search on Bibsonomy ISSCC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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