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1953-1960 (28) 1961-1962 (26) 1963-1964 (27) 1965-1966 (25) 1967 (25) 1968 (23) 1969 (23) 1970-1972 (20) 1973 (31) 1974 (66) 1975 (49) 1976 (67) 1977 (52) 1978 (71) 1979 (62) 1980 (83) 1981 (64) 1982 (88) 1983 (100) 1984 (122) 1985 (193) 1986 (171) 1987 (300) 1988 (431) 1989 (459) 1990 (587) 1991 (414) 1992 (512) 1993 (568) 1994 (740) 1995 (993) 1996 (1011) 1997 (1277) 1998 (1396) 1999 (2138) 2000 (2680) 2001 (3361) 2002 (3942) 2003 (4717) 2004 (6397) 2005 (7657) 2006 (9046) 2007 (9390) 2008 (10911) 2009 (7445) 2010 (1348) 2011 (595) 2012 (587) 2013 (589) 2014 (717) 2015 (680) 2016 (1000) 2017 (472) 2018 (1)
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Found 83787 publication records. Showing 83777 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Renato Fernandes Hentschke, Ricardo Reis A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
7Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Francesco Svelto A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction. Search on Bibsonomy ISSCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
7Matthew Loh, Azita Emami-Neyestanak A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7Tetsuya Iizuka, Norihito Tohge, Satoshi Miura, Yoshimichi Murakami, Toru Nakura, Kunihiro Asada A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking. Search on Bibsonomy ESSCIRC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
7Ja-Yol Lee, Mi-Jeong Park, Byonghoon Mhin, Seongdo Kim, Moon-Yang Park, Hyunku Yu A 4-GHz all digital fractional-N PLL with low-power TDC and big phase-error compensation. Search on Bibsonomy CICC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
7Ja-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, Hyun-Kyu Yu A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7Azaria Paz A 4-State Probablistic Table Approximating All 2-State Probablistic Tables. Search on Bibsonomy A Perspective in Theoretical Computer Science The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
1Mohammad Reza Nakhai, Farrokh Marvasti A 4.1 kb/s hybrid speech coder. Search on Bibsonomy ISCAS (3) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
7Alan W. L. Ng, Shiyuan Zheng, Howard C. Luong A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2nd-order noise-shaping TDC and a transformer-coupled QVCO. Search on Bibsonomy ESSCIRC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7Rakesh Kumar Palani, Ramesh Harjani A 4.6mW, 22dBm IIP3 all MOSCAP based 34-314MHz tunable continuous time filter in 65nm. Search on Bibsonomy CICC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
7I-Ting Lee, Kai-Hui Zeng, Shen-Iuan Liu A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of -252.5 dB. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
7N. Skarmoutsos, E. N. Lallas, Dimitris Syvridis, Thomas Sphicopoulos A 40 Gb/s IM payload/2.5 Gb/s header AOLS technique based on an all fiber realization. Search on Bibsonomy Optical Switching and Networking The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
7Chao-Ching Hung, Shen-Iuan Liu A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
7Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi A 40-nm 640-µm2 45-dB opampless all-digital second-order MASH ΔΣ ADC. Search on Bibsonomy ISCAS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
7Frank Opteynde A 40nm CMOS all-digital fractional-N synthesizer without requiring calibration. Search on Bibsonomy ISSCC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7David D. Wentzloff, Anantha P. Chandrakasan A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Heidi G. Kuehn A 48-bit pseudo-random generator. Search on Bibsonomy Commun. ACM The full citation details ... 1961 DBLP  DOI  BibTeX  RDF
9Suresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Yongjie Cheng, Craig Petrie, Brent Nordick A 4th order single-loop delta-sigma ADC with 8-bit two-step flash quantization. Search on Bibsonomy ISCAS (1) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
7Sally Safwat, Amr Lotfy, Maged Ghoneima, Yehea I. Ismail A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter. Search on Bibsonomy ISCAS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
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