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1953-1960 (28) 1961-1962 (26) 1963-1964 (27) 1965-1966 (25) 1967 (25) 1968 (23) 1969 (23) 1970-1972 (20) 1973 (30) 1974 (66) 1975 (49) 1976 (67) 1977 (52) 1978 (71) 1979 (62) 1980 (83) 1981 (63) 1982 (88) 1983 (100) 1984 (121) 1985 (192) 1986 (171) 1987 (300) 1988 (431) 1989 (458) 1990 (585) 1991 (414) 1992 (511) 1993 (567) 1994 (739) 1995 (993) 1996 (1010) 1997 (1276) 1998 (1396) 1999 (2138) 2000 (2678) 2001 (3360) 2002 (3941) 2003 (4723) 2004 (6387) 2005 (7651) 2006 (9043) 2007 (9387) 2008 (10911) 2009 (7442) 2010 (1345) 2011 (592) 2012 (583) 2013 (587) 2014 (713) 2015 (675) 2016 (645) 2017 (157)
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article(18123) book(20) incollection(2726) inproceedings(62121) phdthesis(26) proceedings(34)
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Found 83060 publication records. Showing 83050 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
7I-Ting Lee, Kai-Hui Zeng, Shen-Iuan Liu A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of -252.5 dB. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
7N. Skarmoutsos, E. N. Lallas, Dimitris Syvridis, Thomas Sphicopoulos A 40 Gb/s IM payload/2.5 Gb/s header AOLS technique based on an all fiber realization. Search on Bibsonomy Optical Switching and Networking The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
7Chao-Ching Hung, Shen-Iuan Liu A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
7Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi A 40-nm 640-µm2 45-dB opampless all-digital second-order MASH ΔΣ ADC. Search on Bibsonomy ISCAS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
7Frank Opteynde A 40nm CMOS all-digital fractional-N synthesizer without requiring calibration. Search on Bibsonomy ISSCC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7David D. Wentzloff, Anantha P. Chandrakasan A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
1Heidi G. Kuehn A 48-bit pseudo-random generator. Search on Bibsonomy Commun. ACM The full citation details ... 1961 DBLP  DOI  BibTeX  RDF
9Suresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Yongjie Cheng, Craig Petrie, Brent Nordick A 4th order single-loop delta-sigma ADC with 8-bit two-step flash quantization. Search on Bibsonomy ISCAS (1) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
7Sally Safwat, Amr Lotfy, Maged Ghoneima, Yehea I. Ismail A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter. Search on Bibsonomy ISCAS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. Search on Bibsonomy ESSCIRC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
1Xianyong Fang, Bin Luo, Haifeng Zhao, Yiwen Zhang A 5-Parameter Bundle Adjustment Method for Image Mosaic. Search on Bibsonomy ACIS-ICIS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
9Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
7Nenad Pavlovic, Jos Bergervoet A 5.3GHz digital-to-time-converter-based fractional-N all-digital PLL. Search on Bibsonomy ISSCC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Le Wang, Parag Upadhyaya, Pinping Sun, Yang Zhang, Deuk Hyoun Heo, Yi-Jan Emery Chen, DongHo Jeong A 5.3GHz low-phase-noise LC VCO with harmonic filtering resistor. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7Kyu-hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. Search on Bibsonomy ISSCC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1T. Gawa, Kenji Taniguchi 0001 A 50% duty-cycle correction circuit for PLL output. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
7Wanghua Wu, Robert Bogdan Staszewski, John R. Long A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
7Wanghua Wu, Xuefei Bai, Robert Bogdan Staszewski, John R. Long A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
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