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1953-1960 (28) 1961-1962 (26) 1963-1964 (27) 1965-1966 (25) 1967 (25) 1968 (23) 1969 (23) 1970-1972 (20) 1973 (30) 1974 (66) 1975 (49) 1976 (67) 1977 (52) 1978 (71) 1979 (62) 1980 (83) 1981 (63) 1982 (88) 1983 (100) 1984 (121) 1985 (192) 1986 (171) 1987 (300) 1988 (431) 1989 (458) 1990 (585) 1991 (414) 1992 (511) 1993 (566) 1994 (739) 1995 (993) 1996 (1009) 1997 (1276) 1998 (1396) 1999 (2138) 2000 (2677) 2001 (3360) 2002 (3941) 2003 (4722) 2004 (6387) 2005 (7649) 2006 (9043) 2007 (9383) 2008 (10905) 2009 (7439) 2010 (1344) 2011 (591) 2012 (581) 2013 (587) 2014 (713) 2015 (675) 2016 (640) 2017 (114)
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Found 82989 publication records. Showing 82979 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
9Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
7Nenad Pavlovic, Jos Bergervoet A 5.3GHz digital-to-time-converter-based fractional-N all-digital PLL. Search on Bibsonomy ISSCC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Le Wang, Parag Upadhyaya, Pinping Sun, Yang Zhang, Deuk Hyoun Heo, Yi-Jan Emery Chen, DongHo Jeong A 5.3GHz low-phase-noise LC VCO with harmonic filtering resistor. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7Kyu-hyoun Kim, Daniel M. Dreps, Frank D. Ferraiolo, Paul W. Coteus, Seongwon Kim, Sergey V. Rylov, Daniel J. Friedman A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. Search on Bibsonomy ISSCC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1T. Gawa, Kenji Taniguchi 0001 A 50% duty-cycle correction circuit for PLL output. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
1Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
7Wanghua Wu, Robert Bogdan Staszewski, John R. Long A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
7Wanghua Wu, Xuefei Bai, Robert Bogdan Staszewski, John R. Long A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Anthony Chan Carusone, David A. Johns A 5th order Gm-C filter in 0.25 ┬Ám CMOS with digitally programmable poles and zeroes. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
2Kiyoko F. Aoki-Kinoshita, Minoru Kanehisa, Ming-Yang Kao, Xiang-Yang Li, Weizhao Wang A 6-Approximation Algorithm for Computing Smallest Common AoN-Supertree with Application to the Reconstruction of Glycan Trees. Search on Bibsonomy ISAAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7I-Ting Lee, Hung-Yu Lu, Shen-Iuan Liu A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
2Xue-mi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7Masum Hossain, Kambiz Kaviani, Barry Daly, Makarand Shirasgaonkar, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Brian Tsang, John C. Eble, Jared Zerbe A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching. Search on Bibsonomy CICC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
7Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
3Zhongtao Fu, John Lee, Alyssa B. Apsel A 6.8GHz low-power and low-phase-noise phase-locked loop design. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Ioannis Caragiannis, Gianpiero Monaco A 6/5-Approximation Algorithm for the Maximum 3-Cover Problem. Search on Bibsonomy MFCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Tyler L. Brandon, John C. Koob, Leendert van den Berg, Zhengang Chen, Amirhossein Alimohammad, Ramkrishna Swamy, Jason Klaus, Stephen Bates, Vincent C. Gaudet, Bruce F. Cockburn, Duncan G. Elliott A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
7Ching-Che Chung, Duo Sheng, Chia-Lin Chang A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology. Search on Bibsonomy IEICE Electronic Express The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim, Hoi-Jun Yoo A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF energy efficient object recognition, multimedia processor, workload-aware dynamic power management
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