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1953-1960 (28) 1961-1962 (26) 1963-1964 (27) 1965-1966 (25) 1967 (25) 1968 (23) 1969 (23) 1970-1972 (20) 1973 (28) 1974 (65) 1975 (48) 1976 (67) 1977 (52) 1978 (71) 1979 (62) 1980 (83) 1981 (63) 1982 (88) 1983 (100) 1984 (121) 1985 (192) 1986 (171) 1987 (300) 1988 (431) 1989 (458) 1990 (585) 1991 (414) 1992 (511) 1993 (566) 1994 (739) 1995 (993) 1996 (1009) 1997 (1276) 1998 (1395) 1999 (2138) 2000 (2677) 2001 (3360) 2002 (3939) 2003 (4722) 2004 (6385) 2005 (7647) 2006 (9042) 2007 (9383) 2008 (10904) 2009 (7438) 2010 (1344) 2011 (591) 2012 (579) 2013 (585) 2014 (708) 2015 (673) 2016 (609) 2017 (41)
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Found 82860 publication records. Showing 82850 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
7Wanghua Wu, Xuefei Bai, Robert Bogdan Staszewski, John R. Long A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
1Anthony Chan Carusone, David A. Johns A 5th order Gm-C filter in 0.25 µm CMOS with digitally programmable poles and zeroes. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
2Kiyoko F. Aoki-Kinoshita, Minoru Kanehisa, Ming-Yang Kao, Xiang-Yang Li, Weizhao Wang A 6-Approximation Algorithm for Computing Smallest Common AoN-Supertree with Application to the Reconstruction of Glycan Trees. Search on Bibsonomy ISAAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7I-Ting Lee, Hung-Yu Lu, Shen-Iuan Liu A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
2Xue-mi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
7Masum Hossain, Kambiz Kaviani, Barry Daly, Makarand Shirasgaonkar, Wayne D. Dettloff, Teva Stone, Kashinath Prabhu, Brian Tsang, John C. Eble, Jared Zerbe A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching. Search on Bibsonomy CICC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
7Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
3Zhongtao Fu, John Lee, Alyssa B. Apsel A 6.8GHz low-power and low-phase-noise phase-locked loop design. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Ioannis Caragiannis, Gianpiero Monaco A 6/5-Approximation Algorithm for the Maximum 3-Cover Problem. Search on Bibsonomy MFCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1Tyler L. Brandon, John C. Koob, Leendert van den Berg, Zhengang Chen, Amirhossein Alimohammad, Ramkrishna Swamy, Jason Klaus, Stephen Bates, Vincent C. Gaudet, Bruce F. Cockburn, Duncan G. Elliott A 600-Mb/s encoder and decoder for low-density parity-check convolutional codes. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
7Ching-Che Chung, Duo Sheng, Chia-Lin Chang A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology. Search on Bibsonomy IEICE Electronic Express The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim, Hoi-Jun Yoo A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF energy efficient object recognition, multimedia processor, workload-aware dynamic power management
7Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops. Search on Bibsonomy VLSIC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
7Shao-Ku Kao, Bo-Jiun Chen, Shen-Iuan Liu A 62.5-625-MHz Anti-Reset All-Digital Delay-Locked Loop. Search on Bibsonomy IEEE Trans. on Circuits and Systems The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
7Seyed Reza Abdollahi, Seid Mehdi Fakhraie, M. Kamaeri, Seyed Ehsan Abdollahi A 68MHz multi-channel all-digital programmable oscillator. Search on Bibsonomy ICECS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
7Kwanyeob Chae, JongRyun Choi, Shinyoung Yi, Won Lee, Sanghoon Joo, Hyunhyuck Kim, Hyungkwon Yi, Yoonjee Nam, Jinho Choi, Sanghune Park, Sanghyun Lee A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology. Search on Bibsonomy ESSCIRC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
7Song-Yu Yang, Wei-Zen Chen, Tai-You Lu A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology. Search on Bibsonomy J. Solid-State Circuits The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
7Song-Yu Yang, Wei-Zen Chen A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
7Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC. Search on Bibsonomy ISSCC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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