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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/iccad/CongK97>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Cheng-Kok_Koh>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Jason_Cong>
foaf:homepage <http://doi.acm.org/10.1145/266388.266618>
foaf:homepage <http://dx.doi.org/10.1145%2F266388.266618>
dc:identifier DBLP conf/iccad/CongK97 (xsd:string)
dc:identifier DOI 10.1145%2F266388.266618 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label Interconnect layout optimization under higher-order RLC model. (xsd:string)
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Cheng-Kok_Koh>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Jason_Cong>
swrc:pages 713-720 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/iccad/CongK97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/iccad/CongK97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/iccad/iccad1997.html#CongK97>
rdfs:seeAlso <http://doi.acm.org/10.1145/266388.266618>
swrc:series <http://dblp.l3s.de/d2r/resource/conferences/iccad>
dc:subject RATS trees, Steiner routings, bounded-radius Steiner trees, circuit optimisation, delay optimization, higher-order RLC model, incremental moment computation algorithm, interconnect layout optimization, nonmonotone signal response, required-arrival-time Steiner trees, resistance-inductance-capacitance circuits, routing area, routing cost, routing topologies, shortest-path Steiner trees, signal delay, signal settling time, topology optimization, voltage overshoot, waveform optimization, waveform quality evaluation, wire-sizing optimization (xsd:string)
dc:title Interconnect layout optimization under higher-order RLC model. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document