Memory organization for video algorithms on programmable signal processors.
Resource URI: http://dblp.l3s.de/d2r/resource/publications/conf/iccd/GreefCM95
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1995
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Memory organization for video algorithms on programmable signal processors.
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digital signal processing chips; memory architecture; storage management; cache storage; image processing; video algorithms; programmable signal processors; DSP; memory-intensive algorithms; video; imaging; mapping; compile-time data caching; performance; buffer sizes; motion estimation type algorithms
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Memory organization for video algorithms on programmable signal processors.
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