An hybrid eDRAM/SRAM macrocell to implement first-level data caches.
Resource URI: http://dblp.l3s.de/d2r/resource/publications/conf/micro/ValeroSPLCLD09
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2009
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An hybrid eDRAM/SRAM macrocell to implement first-level data caches.
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leakage current, retention time, static and dynamic memory cells
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An hybrid eDRAM/SRAM macrocell to implement first-level data caches.
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