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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/vlsid/BansalKKMCR08>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Aditya_Bansal>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Ching-Te_Chuang>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Jae-Joon_Kim>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Keunwoo_Kim>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Saibal_Mukhopadhyay>
foaf:homepage <http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.50>
foaf:homepage <http://dx.doi.org/10.1109%2FVLSI.2008.50>
dc:identifier DBLP conf/vlsid/BansalKKMCR08 (xsd:string)
dc:identifier DOI 10.1109%2FVLSI.2008.50 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. (xsd:string)
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Aditya_Bansal>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Ching-Te_Chuang>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Jae-Joon_Kim>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Keunwoo_Kim>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Saibal_Mukhopadhyay>
swrc:pages 125-130 (xsd:string)
dcterms:partOf <http://dblp.l3s.de/d2r/resource/publications/conf/vlsid/2008>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/vlsid/BansalKKMCR08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/vlsid/BansalKKMCR08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/vlsid/vlsid2008.html#BansalKKMCR08>
rdfs:seeAlso <http://doi.ieeecomputersociety.org/10.1109/VLSI.2008.50>
swrc:series <http://dblp.l3s.de/d2r/resource/conferences/vlsid>
dc:title Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document