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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/jise/LuCL11>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Chao-Hung_Lu>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Chien-Nan_Jimmy_Liu>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Hung-Ming_Chen>
foaf:homepage <http://www.iis.sinica.edu.tw/page/jise/2011/201101_18.html>
dc:identifier DBLP journals/jise/LuCL11 (xsd:string)
dcterms:issued 2011 (xsd:gYear)
swrc:journal <http://dblp.l3s.de/d2r/resource/journals/jise>
rdfs:label Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits. (xsd:string)
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Chao-Hung_Lu>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Chien-Nan_Jimmy_Liu>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Hung-Ming_Chen>
swrc:number 1 (xsd:string)
swrc:pages 287-302 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/jise/LuCL11/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/jise/LuCL11>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/jise/jise27.html#LuCL11>
rdfs:seeAlso <http://www.iis.sinica.edu.tw/page/jise/2011/201101_18.html>
dc:title Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 27 (xsd:string)