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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/NdaiGR10>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Ashish_Goel>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Patrick_Ndai>
foaf:homepage <http://dx.doi.org/10.1109%2FTVLSI.2009.2022628>
foaf:homepage <http://dx.doi.org/10.1109/TVLSI.2009.2022628>
dc:identifier DBLP journals/tvlsi/NdaiGR10 (xsd:string)
dc:identifier DOI 10.1109%2FTVLSI.2009.2022628 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
swrc:journal <http://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors. (xsd:string)
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Ashish_Goel>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Patrick_Ndai>
swrc:number 8 (xsd:string)
swrc:pages 1209-1219 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/NdaiGR10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/NdaiGR10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi18.html#NdaiGR10>
rdfs:seeAlso <http://dx.doi.org/10.1109/TVLSI.2009.2022628>
dc:title A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 18 (xsd:string)