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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tvlsi/WangMDC09>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Francky_Catthoor>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Hua_Wang>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Miguel_Miranda>
dc:creator <http://dblp.l3s.de/d2r/resource/authors/Wim_Dehaene>
foaf:homepage <http://dx.doi.org/10.1109%2FTVLSI.2008.2003169>
foaf:homepage <http://dx.doi.org/10.1109/TVLSI.2008.2003169>
dc:identifier DBLP journals/tvlsi/WangMDC09 (xsd:string)
dc:identifier DOI 10.1109%2FTVLSI.2008.2003169 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
swrc:journal <http://dblp.l3s.de/d2r/resource/journals/tvlsi>
rdfs:label Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning. (xsd:string)
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Francky_Catthoor>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Hua_Wang>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Miguel_Miranda>
foaf:maker <http://dblp.l3s.de/d2r/resource/authors/Wim_Dehaene>
swrc:number 1 (xsd:string)
swrc:pages 117-127 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tvlsi/WangMDC09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tvlsi/WangMDC09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi17.html#WangMDC09>
rdfs:seeAlso <http://dx.doi.org/10.1109/TVLSI.2008.2003169>
dc:title Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 17 (xsd:string)