Pipelining of double precision floating point division and square root operations.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/ACMse/ThakkarE06
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Pipelining of double precision floating point division and square root operations.
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FPGA, division, floating point, pipelining, square root
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Pipelining of double precision floating point division and square root operations.
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