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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/IEEEcit/WangWSW17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jialong_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Li_Shen_0007>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qiong_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhiying_Wang_0003>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FCIT.2017.49>
foaf:homepage <https://doi.org/10.1109/CIT.2017.49>
dc:identifier DBLP conf/IEEEcit/WangWSW17 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FCIT.2017.49 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
rdfs:label A Software-Hardware Co-designed Methodology for Efficient Thread Level Speculation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jialong_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Li_Shen_0007>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qiong_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhiying_Wang_0003>
swrc:pages 184-191 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/IEEEcit/2017>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/IEEEcit/WangWSW17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/IEEEcit/WangWSW17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/IEEEcit/IEEEcit2017.html#WangWSW17>
rdfs:seeAlso <https://doi.org/10.1109/CIT.2017.49>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/IEEEcit>
dc:title A Software-Hardware Co-designed Methodology for Efficient Thread Level Speculation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document