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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/IEEEinteract/ZhouC02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Huiyang_Zhou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thomas_M._Conte>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FINTERA.2002.995845>
foaf:homepage <https://doi.org/10.1109/INTERA.2002.995845>
dc:identifier DBLP conf/IEEEinteract/ZhouC02 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FINTERA.2002.995845 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
rdfs:label Code Size Efficiency in Global Scheduling for ILP Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Huiyang_Zhou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thomas_M._Conte>
swrc:pages 79-90 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/IEEEinteract/2002>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/IEEEinteract/ZhouC02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/IEEEinteract/ZhouC02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/IEEEinteract/IEEEinteract2002.html#ZhouC02>
rdfs:seeAlso <https://doi.org/10.1109/INTERA.2002.995845>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/IEEEinteract>
dc:subject Code Size Efficiency, I-cache Performance, Instruction Level Parallelism (ILP), Code Replication, Tail Duplication, Optimal Code Size Efficiency, Quantitative Measure, Diminishing Returns. (xsd:string)
dc:title Code Size Efficiency in Global Scheduling for ILP Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document