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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aPcsac/ZhangA07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ming_Z._Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vijayan_K._Asari>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-74309-5%5F22>
foaf:homepage <https://doi.org/10.1007/978-3-540-74309-5_22>
dc:identifier DBLP conf/aPcsac/ZhangA07 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-74309-5%5F22 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ming_Z._Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vijayan_K._Asari>
swrc:pages 220-234 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aPcsac/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aPcsac/ZhangA07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aPcsac/ZhangA07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aPcsac/aPcsac2007.html#ZhangA07>
rdfs:seeAlso <https://doi.org/10.1007/978-3-540-74309-5_22>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aPcsac>
dc:subject 2D convolution; log-domain computation; multiplier-less architecture; quadrant symmetric kernels; modularized optimization; FPGA based architecture (xsd:string)
dc:title A Design Methodology for Performance-Resource Optimization of a Generalized 2D Convolution Architecture with Quadrant Symmetric Kernels. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document