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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aPcsac/ZhangZZX06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chengyi_Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hongwei_Zhou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Minxuan_Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zuocheng_Xing>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F11859802%5F62>
foaf:homepage <https://doi.org/10.1007/11859802_62>
dc:identifier DBLP conf/aPcsac/ZhangZZX06 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F11859802%5F62 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chengyi_Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hongwei_Zhou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Minxuan_Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zuocheng_Xing>
swrc:pages 588-594 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aPcsac/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aPcsac/ZhangZZX06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aPcsac/ZhangZZX06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aPcsac/aPcsac2006.html#ZhangZZX06>
rdfs:seeAlso <https://doi.org/10.1007/11859802_62>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aPcsac>
dc:subject Leakage Power, Drowsy cache, Periodically Drowsy Speculative Recover, Adaptive. (xsd:string)
dc:title An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document