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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/acss/MeheraCDP14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arpan_Chakrabarty>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Piyali_Datta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rajat_Kumar_Pal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ranjan_Mehera>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-81-322-1988-0%5F11>
foaf:homepage <https://doi.org/10.1007/978-81-322-1988-0_11>
dc:identifier DBLP conf/acss/MeheraCDP14 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-81-322-1988-0%5F11 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
rdfs:label A 2D Guard Zone Computation Algorithm for Reassignment of Subcircuits to Minimize the Overall Chip Area. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arpan_Chakrabarty>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Piyali_Datta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rajat_Kumar_Pal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ranjan_Mehera>
swrc:pages 183-209 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/acss/2014-2>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/acss/MeheraCDP14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/acss/MeheraCDP14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/acss/acss2014-2.html#MeheraCDP14>
rdfs:seeAlso <https://doi.org/10.1007/978-81-322-1988-0_11>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/acss>
dc:title A 2D Guard Zone Computation Algorithm for Reassignment of Subcircuits to Minimize the Overall Chip Area. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document