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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/acssc/PalchaudhuriD19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anindya_Sundar_Dhar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ayan_Palchaudhuri>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FIEEECONF44664.2019.9049071>
foaf:homepage <https://doi.org/10.1109/IEEECONF44664.2019.9049071>
dc:identifier DBLP conf/acssc/PalchaudhuriD19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FIEEECONF44664.2019.9049071 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
rdfs:label FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anindya_Sundar_Dhar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ayan_Palchaudhuri>
swrc:pages 1555-1559 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/acssc/2019>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/acssc/PalchaudhuriD19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/acssc/PalchaudhuriD19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/acssc/acssc2019.html#PalchaudhuriD19>
rdfs:seeAlso <https://doi.org/10.1109/IEEECONF44664.2019.9049071>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/acssc>
dc:title FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document