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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/aiml2/VR22>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Madhav_Rao>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sanjaya_M._V>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F3564121.3564124>
foaf:homepage <https://doi.org/10.1145/3564121.3564124>
dc:identifier DBLP conf/aiml2/VR22 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F3564121.3564124 (xsd:string)
dcterms:issued 2022 (xsd:gYear)
rdfs:label An hardware accelerator design of Mobile-Net model on FPGA. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Madhav_Rao>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sanjaya_M._V>
swrc:pages 2:1-2:9 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/aiml2/2022>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/aiml2/VR22/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/aiml2/VR22>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/aiml2/aiml2022.html#VR22>
rdfs:seeAlso <https://doi.org/10.1145/3564121.3564124>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/aiml2>
dc:title An hardware accelerator design of Mobile-Net model on FPGA. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document