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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/annes/LaiL95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/K._K._Lai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philip_Heng_Wai_Leong>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FANNES.1995.499437>
foaf:homepage <https://doi.org/10.1109/ANNES.1995.499437>
dc:identifier DBLP conf/annes/LaiL95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FANNES.1995.499437 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label An area efficient implementation of a cellular neural network. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/K._K._Lai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philip_Heng_Wai_Leong>
swrc:pages 51-54 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/annes/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/annes/LaiL95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/annes/LaiL95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/annes/annes1995.html#LaiL95>
rdfs:seeAlso <https://doi.org/10.1109/ANNES.1995.499437>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/annes>
dc:subject cellular neural nets; neural chips; VLSI; cellular logic; circuit analysis computing; edge detection; cellular neural network; area efficient implementation; time multiplexing scheme; higher density implementations; VLSI circuits; simulation; neural circuits; edge detection (xsd:string)
dc:title An area efficient implementation of a cellular neural network. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document