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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/annes/NagamatuIY95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masahiro_Nagamatu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shakeel_Ismail>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Torao_Yanaru>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FANNES.1995.499506>
foaf:homepage <https://doi.org/10.1109/ANNES.1995.499506>
dc:identifier DBLP conf/annes/NagamatuIY95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FANNES.1995.499506 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Lagrangian method for wire routing of layout design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masahiro_Nagamatu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shakeel_Ismail>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Torao_Yanaru>
swrc:pages 350-354 (xsd:string)
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owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/annes/NagamatuIY95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/annes/NagamatuIY95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/annes/annes1995.html#NagamatuIY95>
rdfs:seeAlso <https://doi.org/10.1109/ANNES.1995.499506>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/annes>
dc:subject large scale integration; integrated circuit layout; circuit layout CAD; network routing; neural nets; circuit optimisation; Lagrangian method; wire routing; layout design; LSI layout design; continuous valued constrained optimization problem; continuous valued wires; dynamic equations; neurocomputing; small switchbox routing problems; rip-up reroute maze router (xsd:string)
dc:title Lagrangian method for wire routing of layout design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document