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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/anss/HurS95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stephen_A._Szygenda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Youngmin_Hur>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FSIMSYM.1995.393569>
foaf:homepage <https://doi.org/10.1109/SIMSYM.1995.393569>
dc:identifier DBLP conf/anss/HurS95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FSIMSYM.1995.393569 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Special purpose array processor for digital logic simulation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stephen_A._Szygenda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Youngmin_Hur>
swrc:pages 297-302 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/anss/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/anss/HurS95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/anss/HurS95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/anss/anss1995.html#HurS95>
rdfs:seeAlso <https://doi.org/10.1109/SIMSYM.1995.393569>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/anss>
dc:subject special purpose computers; circuit analysis computing; VLSI; parallel architectures; timing; delays; logic CAD; digital simulation; special purpose array processor; digital logic simulation; fault simulation; large VLSI circuits; compute-intensive tasks; digital analysis; time driven array processor; massively parallel processing element; SIMD architecture; compiled event-driven technology; nominal transport delay timing analysis; delay time order; levelized circuit; massively parallel PE array; MARS accelerator; hardware cost (xsd:string)
dc:title Special purpose array processor for digital logic simulation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document