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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/anss/MollerP96>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chris_H._L._Moller>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gerald_G._Pechanek>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FSIMSYM.1996.492170>
foaf:homepage <https://doi.org/10.1109/SIMSYM.1996.492170>
dc:identifier DBLP conf/anss/MollerP96 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FSIMSYM.1996.492170 (xsd:string)
dcterms:issued 1996 (xsd:gYear)
rdfs:label Architectural simulation system for M.f.a.s.t. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chris_H._L._Moller>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gerald_G._Pechanek>
swrc:pages 221- (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/anss/1996>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/anss/MollerP96/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/anss/MollerP96>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/anss/anss1996.html#MollerP96>
rdfs:seeAlso <https://doi.org/10.1109/SIMSYM.1996.492170>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/anss>
dc:subject virtual machines; pulse transformers; digital signal processing chips; array signal processing; parallel architectures; reconfigurable architectures; instruction sets; architectural simulation system; architecture verification; Mwave folded array signal transform processor; single chip scalable very long instruction word processor array; functional models; independent processes; socket mechanism; simulator performance; execution-unit operations; execution emulation; M.f.a.s.t. processor (xsd:string)
dc:title Architectural simulation system for M.f.a.s.t. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document