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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/anss/VeglisP00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andreas_A._Veglis>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andreas_S._Pombortsis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FSIMSYM.2000.844931>
foaf:homepage <https://doi.org/10.1109/SIMSYM.2000.844931>
dc:identifier DBLP conf/anss/VeglisP00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FSIMSYM.2000.844931 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
rdfs:label Performance Analysis of Multiprocessor Architectures via Analytical Simulation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andreas_A._Veglis>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andreas_S._Pombortsis>
swrc:pages 326-332 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/anss/2000>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/anss/VeglisP00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/anss/VeglisP00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/anss/anss2000.html#VeglisP00>
rdfs:seeAlso <https://doi.org/10.1109/SIMSYM.2000.844931>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/anss>
dc:subject analytical simulation, performance, multiprocessor, MathConnex (xsd:string)
dc:title Performance Analysis of Multiprocessor Architectures via Analytical Simulation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document