High-voltage tolerant switch configuration using standard 3.3-V 0.5-őľm silicon-on-sapphire CMOS transistors. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Asish_Zac_Alex>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Torsten_Lehmann>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FAPCCAS.2014.7032850>
foaf:homepage	<https://doi.org/10.1109/APCCAS.2014.7032850>
dc:identifier	DBLP conf/apccas/AlexL14 (xsd:string)
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dcterms:issued	2014 (xsd:gYear)
rdfs:label	High-voltage tolerant switch configuration using standard 3.3-V 0.5-őľm silicon-on-sapphire CMOS transistors. (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/apccas/apccas2014.html#AlexL14>
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dc:title	High-voltage tolerant switch configuration using standard 3.3-V 0.5-őľm silicon-on-sapphire CMOS transistors. (xsd:string)
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