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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/apccas/HuYLW10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Leibo_Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shaojun_Wei>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shouyi_Yin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yang_Hu_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FAPCCAS.2010.5774752>
foaf:homepage <https://doi.org/10.1109/APCCAS.2010.5774752>
dc:identifier DBLP conf/apccas/HuYLW10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FAPCCAS.2010.5774752 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
rdfs:label Mixed-level modeling for network on chip infrastructure in SoC design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Leibo_Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shaojun_Wei>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shouyi_Yin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yang_Hu_0001>
swrc:pages 911-914 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/apccas/2010>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/apccas/HuYLW10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/apccas/HuYLW10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/apccas/apccas2010.html#HuYLW10>
rdfs:seeAlso <https://doi.org/10.1109/APCCAS.2010.5774752>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/apccas>
dc:title Mixed-level modeling for network on chip infrastructure in SoC design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document