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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/apccas/ZhouZCH06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qiang_Zhou_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xianlong_Hong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yi_Zou>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yici_Cai>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FAPCCAS.2006.342078>
foaf:homepage <https://doi.org/10.1109/APCCAS.2006.342078>
dc:identifier DBLP conf/apccas/ZhouZCH06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FAPCCAS.2006.342078 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
rdfs:label Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qiang_Zhou_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xianlong_Hong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yi_Zou>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yici_Cai>
swrc:pages 1635-1638 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/apccas/2006>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/apccas/ZhouZCH06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/apccas/ZhouZCH06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/apccas/apccas2006.html#ZhouZCH06>
rdfs:seeAlso <https://doi.org/10.1109/APCCAS.2006.342078>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/apccas>
dc:title Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document