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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/applepies/MarinoFMBBILMAR23>
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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Federico_Vittorio_Lupo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Francesco_Fienga>
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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marco_Arzeo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michele_Riccio>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Oleg_A._Mukhanov>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vincenzo_Romano_Marrazzo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-031-48121-5%5F12>
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dc:identifier DBLP conf/applepies/MarinoFMBBILMAR23 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-031-48121-5%5F12 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
rdfs:label Efficient Optimization of SFQ-Based Logic Circuits: Introducing a Novel Methodology for Performance and Design Enhancement. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alessandro_Borghese>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrea_Irace>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Federico_Vittorio_Lupo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Francesco_Fienga>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Giovanni_Breglio>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Laura_Di_Marino>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marco_Arzeo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michele_Riccio>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Oleg_A._Mukhanov>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vincenzo_Romano_Marrazzo>
swrc:pages 80-86 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1007/978-3-031-48121-5_12>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/applepies>
dc:title Efficient Optimization of SFQ-Based Logic Circuits: Introducing a Novel Methodology for Performance and Design Enhancement. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document