[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/appt/GuoWZS13>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Guoyin_Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tianxiang_Sui>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yanxia_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhenhua_Guo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-642-45293-2%5F23>
foaf:homepage <https://doi.org/10.1007/978-3-642-45293-2_23>
dc:identifier DBLP conf/appt/GuoWZS13 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-642-45293-2%5F23 (xsd:string)
dcterms:issued 2013 (xsd:gYear)
rdfs:label An Improved FPGAs-Based Loop Pipeline Scheduling Algorithm for Reconfigurable Compiler. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Guoyin_Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tianxiang_Sui>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yanxia_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhenhua_Guo>
swrc:pages 307-318 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/appt/2013>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/appt/GuoWZS13/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/appt/GuoWZS13>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/appt/appt2013.html#GuoWZS13>
rdfs:seeAlso <https://doi.org/10.1007/978-3-642-45293-2_23>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/appt>
dc:title An Improved FPGAs-Based Loop Pipeline Scheduling Algorithm for Reconfigurable Compiler. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document