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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/appt/ZhangWXWW09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Dongsheng_Wang_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Haixia_Wang_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jinglei_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xi_Zhang_0008>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yibo_Xue>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-642-03644-6%5F4>
foaf:homepage <https://doi.org/10.1007/978-3-642-03644-6_4>
dc:identifier DBLP conf/appt/ZhangWXWW09 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-642-03644-6%5F4 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label A Novel Cache Organization for Tiled Chip Multiprocessor. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Dongsheng_Wang_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Haixia_Wang_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jinglei_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xi_Zhang_0008>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yibo_Xue>
swrc:pages 41-53 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/appt/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/appt/ZhangWXWW09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/appt/ZhangWXWW09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/appt/appt2009.html#ZhangWXWW09>
rdfs:seeAlso <https://doi.org/10.1007/978-3-642-03644-6_4>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/appt>
dc:subject Chip Multiprocessor(CMP); Tiled Architecture; Multi-level Directory; Cache Organization (xsd:string)
dc:title A Novel Cache Organization for Tiled Chip Multiprocessor. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document