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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/arc/ParkD07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Joonseok_Park>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pedro_C._Diniz>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-71431-6%5F10>
foaf:homepage <https://doi.org/10.1007/978-3-540-71431-6_10>
dc:identifier DBLP conf/arc/ParkD07 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-71431-6%5F10 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
rdfs:label Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Joonseok_Park>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pedro_C._Diniz>
swrc:pages 97-109 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/arc/2007>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/arc/ParkD07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/arc/ParkD07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/arc/arc2007.html#ParkD07>
rdfs:seeAlso <https://doi.org/10.1007/978-3-540-71431-6_10>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/arc>
dc:subject Field Programmable Gate Arrays (FPGA); Reconfigurable Computing; data reuse; scalar replacement; loop splitting; loop interchange (xsd:string)
dc:title Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document