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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/arc/Sterpone09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luca_Sterpone>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-642-00641-8%5F11>
foaf:homepage <https://doi.org/10.1007/978-3-642-00641-8_11>
dc:identifier DBLP conf/arc/Sterpone09 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-642-00641-8%5F11 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
rdfs:label Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luca_Sterpone>
swrc:pages 85-96 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/arc/2009>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/arc/Sterpone09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/arc/Sterpone09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/arc/arc2009.html#Sterpone09>
rdfs:seeAlso <https://doi.org/10.1007/978-3-642-00641-8_11>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/arc>
dc:subject FPGA; fault tolerance; Single Event Upset; Timing-driven Placement; Triple Modular Redundancy (xsd:string)
dc:title Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document