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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/arc/SunnyDMC21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chilankamol_Sunny>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kevin_J._M._Martin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philippe_Coussy>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Satyajit_Das>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-030-79025-7%5F5>
foaf:homepage <https://doi.org/10.1007/978-3-030-79025-7_5>
dc:identifier DBLP conf/arc/SunnyDMC21 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-030-79025-7%5F5 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label Hardware Based Loop Optimization for CGRA Architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chilankamol_Sunny>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kevin_J._M._Martin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philippe_Coussy>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Satyajit_Das>
swrc:pages 65-80 (xsd:string)
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owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/arc/SunnyDMC21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/arc/SunnyDMC21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/arc/arc2021.html#SunnyDMC21>
rdfs:seeAlso <https://doi.org/10.1007/978-3-030-79025-7_5>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/arc>
dc:title Hardware Based Loop Optimization for CGRA Architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document