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dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shinya_Takamaeda-Yamazaki>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-319-16214-0%5F42>
foaf:homepage <https://doi.org/10.1007/978-3-319-16214-0_42>
dc:identifier DBLP conf/arc/Takamaeda-Yamazaki15 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-319-16214-0%5F42 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
rdfs:label Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shinya_Takamaeda-Yamazaki>
swrc:pages 451-460 (xsd:string)
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rdfs:seeAlso <https://doi.org/10.1007/978-3-319-16214-0_42>
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dc:title Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document