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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/arc/WielgoszJW08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ernest_Jamro>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kazimierz_Wiatr>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Maciej_Wielgosz>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-540-78610-8%5F28>
foaf:homepage <https://doi.org/10.1007/978-3-540-78610-8_28>
dc:identifier DBLP conf/arc/WielgoszJW08 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-540-78610-8%5F28 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
rdfs:label Highly efficient structure of 64-bit exponential function implemented in FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ernest_Jamro>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kazimierz_Wiatr>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Maciej_Wielgosz>
swrc:pages 272-277 (xsd:string)
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owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/arc/WielgoszJW08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/arc/WielgoszJW08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/arc/arc2008.html#WielgoszJW08>
rdfs:seeAlso <https://doi.org/10.1007/978-3-540-78610-8_28>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/arc>
dc:subject HPRC (High Performance Reconfigurable Computing); FPGA; elementary function; exponent function (xsd:string)
dc:title Highly efficient structure of 64-bit exponential function implemented in FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document