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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/arc/WitschenWNBP21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Arne_Bockhorn>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Linus_Witschen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marco_Platzner>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masood_Raeisi_Nafchi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tobias_Wiersema>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2F978-3-030-79025-7%5F4>
foaf:homepage <https://doi.org/10.1007/978-3-030-79025-7_4>
dc:identifier DBLP conf/arc/WitschenWNBP21 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2F978-3-030-79025-7%5F4 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
rdfs:label Timing Optimization for Virtual FPGA Configurations. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Arne_Bockhorn>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Linus_Witschen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marco_Platzner>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masood_Raeisi_Nafchi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tobias_Wiersema>
swrc:pages 50-64 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/arc/2021>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/arc/WitschenWNBP21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/arc/WitschenWNBP21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/arc/arc2021.html#WitschenWNBP21>
rdfs:seeAlso <https://doi.org/10.1007/978-3-030-79025-7_4>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/arc>
dc:title Timing Optimization for Virtual FPGA Configurations. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document