Abacus: a 1024 processor 8 ns SIMD array.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/arvlsi/BolotskiSVAK95
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Abacus: a 1024 processor 8 ns SIMD array.
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parallel architectures; reconfigurable architectures; VLSI; real-time systems; computer vision; bit-slice computers; Abacus; SIMD array; microarchitecture; reconfigurable bit-parallel array; communication primitives; VLSI implementation; system-level design issues; real-time early vision processing; bit-slice processing element; 8 ns
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Abacus: a 1024 processor 8 ns SIMD array.
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