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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/arvlsi/DeWeerthPSSC97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_E._Schimmel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Girish_N._Patel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mario_F._Simoni>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ronald_L._Calabrese>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stephen_P._DeWeerth>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FARVLSI.1997.634854>
foaf:homepage <https://doi.org/10.1109/ARVLSI.1997.634854>
dc:identifier DBLP conf/arvlsi/DeWeerthPSSC97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FARVLSI.1997.634854 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
rdfs:label A VLSI Architecture for Modeling Intersegmental Coordination. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_E._Schimmel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Girish_N._Patel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mario_F._Simoni>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ronald_L._Calabrese>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stephen_P._DeWeerth>
swrc:pages 182-200 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/arvlsi/1997>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/arvlsi/DeWeerthPSSC97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/arvlsi/DeWeerthPSSC97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/arvlsi/arvlsi1997.html#DeWeerthPSSC97>
rdfs:seeAlso <https://doi.org/10.1109/ARVLSI.1997.634854>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/arvlsi>
dc:title A VLSI Architecture for Modeling Intersegmental Coordination. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document