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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/arvlsi/DhaneshaFH95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/H._Dhanesha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/K._Falakshahi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mark_Horowitz>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FARVLSI.1995.515617>
foaf:homepage <https://doi.org/10.1109/ARVLSI.1995.515617>
dc:identifier DBLP conf/arvlsi/DhaneshaFH95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FARVLSI.1995.515617 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Array-of-arrays architecture for parallel floating point multiplication. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/H._Dhanesha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/K._Falakshahi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mark_Horowitz>
swrc:pages 150-157 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/arvlsi/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/arvlsi/DhaneshaFH95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/arvlsi/DhaneshaFH95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/arvlsi/arvlsi1995.html#DhaneshaFH95>
rdfs:seeAlso <https://doi.org/10.1109/ARVLSI.1995.515617>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/arvlsi>
dc:subject parallel architectures; floating point arithmetic; multiplying circuits; array-of-arrays architecture; parallel floating point multiplication; synergy; trees; mantissa path; IEEE standard 754; Verilog; dual-rail domino; HSpice simulation; capacitive load model; CMOS technology; latency; 53 bit; 1 micron; 10 ns; 4.3 V; 120 C (xsd:string)
dc:title Array-of-arrays architecture for parallel floating point multiplication. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document