Efficient retiming under a general delay model. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/conf/arvlsi/LalgudiP95>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Kumar_N._Lalgudi>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Marios_C._Papaefthymiou>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FARVLSI.1995.515633>
foaf:homepage	<https://doi.org/10.1109/ARVLSI.1995.515633>
dc:identifier	DBLP conf/arvlsi/LalgudiP95 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FARVLSI.1995.515633 (xsd:string)
dcterms:issued	1995 (xsd:gYear)
rdfs:label	Efficient retiming under a general delay model. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Kumar_N._Lalgudi>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Marios_C._Papaefthymiou>
swrc:pages	368-382 (xsd:string)
dcterms:partOf	<https://dblp.l3s.de/d2r/resource/publications/conf/arvlsi/1995>
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/conf/arvlsi/LalgudiP95/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/conf/arvlsi/LalgudiP95>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/conf/arvlsi/arvlsi1995.html#LalgudiP95>
rdfs:seeAlso	<https://doi.org/10.1109/ARVLSI.1995.515633>
swrc:series	<https://dblp.l3s.de/d2r/resource/conferences/arvlsi>
dc:subject	logic design; timing; delays; linear programming; integer programming; logic circuits; retiming algorithm; general delay model; logic design; edge-triggered circuits; load-dependent gate delays; register delays; interconnect delays; clock skew; integer linear programming constraints; propagation delays; integer phonotonic programming formulation (xsd:string)
dc:title	Efficient retiming under a general delay model. (xsd:string)
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