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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/arvlsi/MonteiroRDG95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Abhijit_Ghosh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/John_Rinderknecht>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Monteiro_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Devadas>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FARVLSI.1995.515637>
foaf:homepage <https://doi.org/10.1109/ARVLSI.1995.515637>
dc:identifier DBLP conf/arvlsi/MonteiroRDG95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FARVLSI.1995.515637 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Optimization of combinational and sequential logic circuits for low power using precomputation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Abhijit_Ghosh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/John_Rinderknecht>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_Monteiro_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Devadas>
swrc:pages 430-444 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/arvlsi/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/arvlsi/MonteiroRDG95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/arvlsi/MonteiroRDG95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/arvlsi/arvlsi1995.html#MonteiroRDG95>
rdfs:seeAlso <https://doi.org/10.1109/ARVLSI.1995.515637>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/arvlsi>
dc:subject circuit optimisation; logic design; combinational circuits; sequential circuits; VLSI; CMOS logic circuits; integrated circuit design; combinational logic circuits; sequential logic circuits; low power optimisation; precomputation; logic optimization technique; precomputation architectures; logic synthesis methods; transmission gates; transparent latches; clock cycle; switching activity reduction; power dissipation reduction (xsd:string)
dc:title Optimization of combinational and sequential logic circuits for low power using precomputation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document