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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/conf/arvlsi/MyersRM95>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chris_J._Myers>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Teresa_H.-Y._Meng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tomas_Rokicki>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FARVLSI.1995.515610>
foaf:homepage <https://doi.org/10.1109/ARVLSI.1995.515610>
dc:identifier DBLP conf/arvlsi/MyersRM95 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FARVLSI.1995.515610 (xsd:string)
dcterms:issued 1995 (xsd:gYear)
rdfs:label Automatic synthesis of gate-level timed circuits with choice. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chris_J._Myers>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Teresa_H.-Y._Meng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tomas_Rokicki>
swrc:pages 42-58 (xsd:string)
dcterms:partOf <https://dblp.l3s.de/d2r/resource/publications/conf/arvlsi/1995>
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/conf/arvlsi/MyersRM95/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/conf/arvlsi/MyersRM95>
rdfs:seeAlso <http://dblp.uni-trier.de/db/conf/arvlsi/arvlsi1995.html#MyersRM95>
rdfs:seeAlso <https://doi.org/10.1109/ARVLSI.1995.515610>
swrc:series <https://dblp.l3s.de/d2r/resource/conferences/arvlsi>
dc:subject logic CAD; circuit CAD; asynchronous circuits; timing; state-space methods; cellular arrays; logic arrays; gate-level timed circuits; CAD tool; automatic synthesis; C-elements; OR gates; AND gates; asynchronous circuits; explicit timing information; textual specification; conditional operation; graphical representation; reachable state space; semi-custom components; standard-cells; gate-arrays; circuit complexity (xsd:string)
dc:title Automatic synthesis of gate-level timed circuits with choice. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:InProceedings
rdf:type foaf:Document