HAL: heuristic algorithms for layout synthesis.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/arvlsi/RekhiT95
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1995
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HAL: heuristic algorithms for layout synthesis.
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circuit layout CAD; logic CAD; graph theory; CMOS logic circuits; network topology; heuristic algorithms; layout synthesis; graph theory based algorithms; leaf cells; common poly gates; 1-1/2-d layout style; common circuit nodes; transistor sets; layout area; symbolic layouts; CMOS circuits; static dual type; static CMOS circuitry; pullup network; pulldown network; dynamic logic styles; GENIE; run time efficient
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HAL: heuristic algorithms for layout synthesis.
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