The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/arvlsi/YamauchiHO97
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/arvlsi/YamauchiHO97
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kunle_Olukotun
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Lance_Hammond
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Tadaaki_Yamauchi
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FARVLSI.1997.634862
>
foaf:
homepage
<
https://doi.org/10.1109/ARVLSI.1997.634862
>
dc:
identifier
DBLP conf/arvlsi/YamauchiHO97
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FARVLSI.1997.634862
(xsd:string)
dcterms:
issued
1997
(xsd:gYear)
rdfs:
label
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kunle_Olukotun
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Lance_Hammond
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Tadaaki_Yamauchi
>
swrc:
pages
303-319
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/arvlsi/1997
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/arvlsi/YamauchiHO97/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/arvlsi/YamauchiHO97
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/arvlsi/arvlsi1997.html#YamauchiHO97
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ARVLSI.1997.634862
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/arvlsi
>
dc:
title
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document