Real time all intra HEVC HD encoder on FPGA.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/conf/asap/AtapattuLMPP16
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/conf/asap/AtapattuLMPP16
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ajith_Pasqual
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ishantha_Perera
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Namitha_Liyanage
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Nisal_Menuka
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Sachille_Atapattu
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FASAP.2016.7760792
>
foaf:
homepage
<
https://doi.org/10.1109/ASAP.2016.7760792
>
dc:
identifier
DBLP conf/asap/AtapattuLMPP16
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2FASAP.2016.7760792
(xsd:string)
dcterms:
issued
2016
(xsd:gYear)
rdfs:
label
Real time all intra HEVC HD encoder on FPGA.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ajith_Pasqual
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ishantha_Perera
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Namitha_Liyanage
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Nisal_Menuka
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Sachille_Atapattu
>
swrc:
pages
191-195
(xsd:string)
dcterms:
partOf
<
https://dblp.l3s.de/d2r/resource/publications/conf/asap/2016
>
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/conf/asap/AtapattuLMPP16/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/conf/asap/AtapattuLMPP16
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/conf/asap/asap2016.html#AtapattuLMPP16
>
rdfs:
seeAlso
<
https://doi.org/10.1109/ASAP.2016.7760792
>
swrc:
series
<
https://dblp.l3s.de/d2r/resource/conferences/asap
>
dc:
title
Real time all intra HEVC HD encoder on FPGA.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:InProceedings
rdf:
type
foaf:Document